1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 < %s | FileCheck %s -check-prefix=CHECK 3 4define void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { 5; CHECK-LABEL: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset: 6; CHECK: ; %bb.0: 7; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 8; CHECK-NEXT: buffer_atomic_add_f32 v0, v[1:2], s[16:19], s20 idxen offen offset:24 9; CHECK-NEXT: s_waitcnt vmcnt(0) 10; CHECK-NEXT: s_setpc_b64 s[30:31] 11 %voffset.add = add i32 %voffset, 24 12 %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0) 13 ret void 14} 15 16; Natural mapping, no voffset 17define void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) { 18; CHECK-LABEL: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset: 19; CHECK: ; %bb.0: 20; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 21; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[16:19], s20 idxen 22; CHECK-NEXT: s_waitcnt vmcnt(0) 23; CHECK-NEXT: s_setpc_b64 s[30:31] 24 %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 0) 25 ret void 26} 27 28define void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { 29; CHECK-LABEL: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc: 30; CHECK: ; %bb.0: 31; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 32; CHECK-NEXT: buffer_atomic_add_f32 v0, v[1:2], s[16:19], s20 idxen offen slc 33; CHECK-NEXT: s_waitcnt vmcnt(0) 34; CHECK-NEXT: s_setpc_b64 s[30:31] 35 %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 2) 36 ret void 37} 38 39define void @struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { 40; CHECK-LABEL: struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset: 41; CHECK: ; %bb.0: 42; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 43; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, v[1:2], s[16:19], s20 idxen offen offset:24 44; CHECK-NEXT: s_waitcnt vmcnt(0) 45; CHECK-NEXT: s_setpc_b64 s[30:31] 46 %voffset.add = add i32 %voffset, 24 47 %ret = call <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0) 48 ret void 49} 50 51declare float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32, i32 immarg) #0 52declare <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32 immarg) #0 53 54attributes #0 = { nounwind } 55