1; RUN: opt -mtriple=amdgcn-- -passes='cgscc(inline)' -S -amdgpu-inline-max-bb=2 %s | FileCheck %s --check-prefix=NOINL 2; RUN: opt -mtriple=amdgcn-- -passes='cgscc(inline)' -S -amdgpu-inline-max-bb=3 %s | FileCheck %s --check-prefix=INL 3; RUN: opt -mtriple=amdgcn-- -passes=inline -S -amdgpu-inline-max-bb=2 %s | FileCheck %s --check-prefix=NOINL 4; RUN: opt -mtriple=amdgcn-- -passes=inline -S -amdgpu-inline-max-bb=3 %s | FileCheck %s --check-prefix=INL 5 6define i32 @callee(i32 %x) { 7entry: 8 %cc = icmp eq i32 %x, 1 9 br i1 %cc, label %ret_res, label %mulx 10 11mulx: 12 %mul1 = mul i32 %x, %x 13 %mul2 = mul i32 %mul1, %x 14 %mul3 = mul i32 %mul1, %mul2 15 %mul4 = mul i32 %mul3, %mul2 16 %mul5 = mul i32 %mul4, %mul3 17 br label %ret_res 18 19ret_res: 20 %r = phi i32 [ %mul5, %mulx ], [ %x, %entry ] 21 ret i32 %r 22} 23 24; INL-LABEL: @caller 25; NOINL-LABEL: @caller 26; INL: mul i32 27; INL-NOT: call i32 28; NOINL-NOT: mul i32 29; NOINL: call i32 30 31define amdgpu_kernel void @caller(i32 %x) { 32 %res = call i32 @callee(i32 %x) 33 store volatile i32 %res, ptr addrspace(1) undef 34 ret void 35} 36 37 38; inlinehint 39define i32 @callee_hint(i32 %x) #0 { 40entry: 41 %cc = icmp eq i32 %x, 1 42 br i1 %cc, label %ret_res, label %mulx 43 44mulx: 45 %mul1 = mul i32 %x, %x 46 %mul2 = mul i32 %mul1, %x 47 %mul3 = mul i32 %mul1, %mul2 48 %mul4 = mul i32 %mul3, %mul2 49 %mul5 = mul i32 %mul4, %mul3 50 br label %ret_res 51 52ret_res: 53 %r = phi i32 [ %mul5, %mulx ], [ %x, %entry ] 54 ret i32 %r 55} 56 57; INL-LABEL: @caller_hint 58; NOINL-LABEL: @caller_hint 59; INL: mul i32 60; INL-NOT: call i32 61; NOINL: mul i32 62; NOINL-NOT: call i32 63 64define amdgpu_kernel void @caller_hint(i32 %x) { 65 %res = call i32 @callee_hint(i32 %x) 66 store volatile i32 %res, ptr addrspace(1) undef 67 ret void 68} 69 70attributes #0 = { inlinehint } 71