1; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s 2 3; The first image store and the second image load use the same descriptor and 4; the same coordinate. Check that they do not get swapped by the machine 5; instruction scheduler. 6 7; GCN-LABEL: {{^}}_amdgpu_cs_main: 8; GCN: image_load 9; GCN: image_store 10; GCN: image_load 11; GCN: image_store 12 13define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <3 x i32> inreg %arg3, i32 inreg %arg4, <3 x i32> %arg5) local_unnamed_addr #0 { 14.entry: 15 %tmp = call i64 @llvm.amdgcn.s.getpc() #1 16 %tmp6 = bitcast i64 %tmp to <2 x i32> 17 %.0.vec.insert = insertelement <2 x i32> undef, i32 %arg2, i32 0 18 %.4.vec.insert = shufflevector <2 x i32> %.0.vec.insert, <2 x i32> %tmp6, <2 x i32> <i32 0, i32 3> 19 %tmp7 = bitcast <2 x i32> %.4.vec.insert to i64 20 %tmp8 = inttoptr i64 %tmp7 to ptr addrspace(4) 21 %tmp9 = add <3 x i32> %arg3, %arg5 22 %tmp10 = getelementptr [4294967295 x i8], ptr addrspace(4) %tmp8, i64 0, i64 32 23 %tmp12 = load <8 x i32>, ptr addrspace(4) %tmp10, align 16 24 %tmp13.0 = extractelement <3 x i32> %tmp9, i32 0 25 %tmp13.1 = extractelement <3 x i32> %tmp9, i32 1 26 %tmp14 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %tmp13.0, i32 %tmp13.1, <8 x i32> %tmp12, i32 0, i32 0) #0 27 %tmp15 = inttoptr i64 %tmp7 to ptr addrspace(4) 28 %tmp16 = load <8 x i32>, ptr addrspace(4) %tmp15, align 16 29 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %tmp14, i32 15, i32 %tmp13.0, i32 %tmp13.1, <8 x i32> %tmp16, i32 0, i32 0) #0 30 %tmp17 = load <8 x i32>, ptr addrspace(4) %tmp15, align 16 31 %tmp18 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 165, i32 %tmp13.0, i32 %tmp13.1, <8 x i32> %tmp17, i32 0, i32 0) #0 32 %tmp19 = getelementptr [4294967295 x i8], ptr addrspace(4) %tmp8, i64 0, i64 64 33 %tmp21 = load <8 x i32>, ptr addrspace(4) %tmp19, align 16 34 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %tmp18, i32 15, i32 %tmp13.0, i32 %tmp13.1, <8 x i32> %tmp21, i32 0, i32 0) #0 35 ret void 36} 37 38; Function Attrs: nounwind readnone speculatable 39declare i64 @llvm.amdgcn.s.getpc() #1 40 41; Function Attrs: nounwind readonly 42declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #2 43 44; Function Attrs: nounwind writeonly 45declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32, i32, i32, <8 x i32>, i32, i32) #3 46 47attributes #0 = { nounwind } 48attributes #1 = { nounwind readnone speculatable } 49attributes #2 = { nounwind readonly } 50attributes #3 = { nounwind writeonly } 51 52!0 = !{} 53