1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 3 4define amdgpu_ps void @i1_copy_from_loop(ptr addrspace(8) inreg %rsrc, i32 %tid) { 5; SI-LABEL: i1_copy_from_loop: 6; SI: ; %bb.0: ; %entry 7; SI-NEXT: s_mov_b32 s14, 0 8; SI-NEXT: s_mov_b64 s[4:5], 0 9; SI-NEXT: ; implicit-def: $sgpr6_sgpr7 10; SI-NEXT: ; implicit-def: $sgpr8_sgpr9 11; SI-NEXT: s_branch .LBB0_3 12; SI-NEXT: .LBB0_1: ; in Loop: Header=BB0_3 Depth=1 13; SI-NEXT: ; implicit-def: $sgpr14 14; SI-NEXT: .LBB0_2: ; %Flow 15; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 16; SI-NEXT: s_and_b64 s[12:13], exec, s[8:9] 17; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[4:5] 18; SI-NEXT: s_andn2_b64 s[6:7], s[6:7], exec 19; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec 20; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] 21; SI-NEXT: s_andn2_b64 exec, exec, s[4:5] 22; SI-NEXT: s_cbranch_execz .LBB0_7 23; SI-NEXT: .LBB0_3: ; %for.body 24; SI-NEXT: ; =>This Inner Loop Header: Depth=1 25; SI-NEXT: s_cmp_lt_u32 s14, 4 26; SI-NEXT: s_cselect_b64 s[10:11], -1, 0 27; SI-NEXT: s_or_b64 s[8:9], s[8:9], exec 28; SI-NEXT: s_cmp_gt_u32 s14, 3 29; SI-NEXT: s_cbranch_scc1 .LBB0_1 30; SI-NEXT: ; %bb.4: ; %mid.loop 31; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 32; SI-NEXT: v_mov_b32_e32 v1, s14 33; SI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 idxen offen 34; SI-NEXT: s_mov_b64 s[10:11], -1 35; SI-NEXT: s_waitcnt vmcnt(0) 36; SI-NEXT: v_cmp_le_f32_e32 vcc, 0, v1 37; SI-NEXT: s_mov_b64 s[8:9], -1 38; SI-NEXT: s_and_saveexec_b64 s[12:13], vcc 39; SI-NEXT: s_cbranch_execz .LBB0_6 40; SI-NEXT: ; %bb.5: ; %end.loop 41; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 42; SI-NEXT: s_add_i32 s14, s14, 1 43; SI-NEXT: s_xor_b64 s[8:9], exec, -1 44; SI-NEXT: .LBB0_6: ; %Flow1 45; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 46; SI-NEXT: s_or_b64 exec, exec, s[12:13] 47; SI-NEXT: s_branch .LBB0_2 48; SI-NEXT: .LBB0_7: ; %for.end 49; SI-NEXT: s_or_b64 exec, exec, s[4:5] 50; SI-NEXT: s_and_saveexec_b64 s[0:1], s[6:7] 51; SI-NEXT: s_cbranch_execz .LBB0_9 52; SI-NEXT: ; %bb.8: ; %if 53; SI-NEXT: exp mrt0 v0, v0, v0, v0 done vm 54; SI-NEXT: .LBB0_9: ; %end 55; SI-NEXT: s_endpgm 56entry: 57 br label %for.body 58 59for.body: 60 %i = phi i32 [0, %entry], [%i.inc, %end.loop] 61 %cc = icmp ult i32 %i, 4 62 br i1 %cc, label %mid.loop, label %for.end 63 64mid.loop: 65 %v = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %tid, i32 %i, i32 0, i32 0) 66 %cc2 = fcmp oge float %v, 0.0 67 br i1 %cc2, label %end.loop, label %for.end 68 69end.loop: 70 %i.inc = add i32 %i, 1 71 br label %for.body 72 73for.end: 74 br i1 %cc, label %if, label %end 75 76if: 77 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float undef, float undef, float undef, float undef, i1 true, i1 true) 78 br label %end 79 80end: 81 ret void 82} 83 84declare float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8), i32, i32, i32, i32 immarg) #0 85declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1 86 87attributes #0 = { nounwind memory(argmem: read) } 88attributes #1 = { nounwind inaccessiblememonly } 89