xref: /llvm-project/llvm/test/CodeGen/AMDGPU/gds-atomic.ll (revision f93aa5157a3317b24cff660ac972814ee9ed4dbc)
1; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
2; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
5; RUN: llc -mtriple=amdgcn -mcpu=gfx9-generic --amdhsa-code-object-version=6 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
6
7; FUNC-LABEL: {{^}}atomic_add_ret_gds:
8; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
9; GCN-DAG: s_movk_i32 m0, 0x1000
10; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v[[OFF]], v{{[0-9]+}} gds
11define amdgpu_kernel void @atomic_add_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
12  %val = atomicrmw volatile add ptr addrspace(2) %gds, i32 5 acq_rel
13  store i32 %val, ptr addrspace(1) %out
14  ret void
15}
16
17; FUNC-LABEL: {{^}}atomic_add_ret_gds_const_offset:
18; GCN: s_movk_i32 m0, 0x80
19; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20 gds
20define amdgpu_kernel void @atomic_add_ret_gds_const_offset(ptr addrspace(1) %out, ptr addrspace(2) %gds) #0 {
21  %gep = getelementptr i32, ptr addrspace(2) %gds, i32 5
22  %val = atomicrmw volatile add ptr addrspace(2) %gep, i32 5 acq_rel
23  store i32 %val, ptr addrspace(1) %out
24  ret void
25}
26
27; FUNC-LABEL: {{^}}atomic_sub_ret_gds:
28; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
29; GCN-DAG: s_movk_i32 m0, 0x1000
30; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v[[OFF]], v{{[0-9]+}} gds
31define amdgpu_kernel void @atomic_sub_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
32  %val = atomicrmw sub ptr addrspace(2) %gds, i32 5 acq_rel
33  store i32 %val, ptr addrspace(1) %out
34  ret void
35}
36
37; FUNC-LABEL: {{^}}atomic_and_ret_gds:
38; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
39; GCN-DAG: s_movk_i32 m0, 0x1000
40; GCN: ds_and_rtn_b32 v{{[0-9]+}}, v[[OFF]], v{{[0-9]+}} gds
41define amdgpu_kernel void @atomic_and_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
42  %val = atomicrmw and ptr addrspace(2) %gds, i32 5 acq_rel
43  store i32 %val, ptr addrspace(1) %out
44  ret void
45}
46
47; FUNC-LABEL: {{^}}atomic_or_ret_gds:
48; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
49; GCN-DAG: s_movk_i32 m0, 0x1000
50; GCN: ds_or_rtn_b32 v{{[0-9]+}}, v[[OFF]], v{{[0-9]+}} gds
51define amdgpu_kernel void @atomic_or_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
52  %val = atomicrmw or ptr addrspace(2) %gds, i32 5 acq_rel
53  store i32 %val, ptr addrspace(1) %out
54  ret void
55}
56
57; FUNC-LABEL: {{^}}atomic_xor_ret_gds:
58; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
59; GCN-DAG: s_movk_i32 m0, 0x1000
60; GCN: ds_xor_rtn_b32 v{{[0-9]+}}, v[[OFF]], v{{[0-9]+}} gds
61define amdgpu_kernel void @atomic_xor_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
62  %val = atomicrmw xor ptr addrspace(2) %gds, i32 5 acq_rel
63  store i32 %val, ptr addrspace(1) %out
64  ret void
65}
66
67; FUNC-LABEL: {{^}}atomic_umin_ret_gds:
68; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
69; GCN-DAG: s_movk_i32 m0, 0x1000
70; GCN: ds_min_rtn_u32 v{{[0-9]+}}, v[[OFF]], v{{[0-9]+}} gds
71define amdgpu_kernel void @atomic_umin_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
72  %val = atomicrmw umin ptr addrspace(2) %gds, i32 5 acq_rel
73  store i32 %val, ptr addrspace(1) %out
74  ret void
75}
76
77; FUNC-LABEL: {{^}}atomic_umax_ret_gds:
78; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
79; GCN-DAG: s_movk_i32 m0, 0x1000
80; GCN: ds_max_rtn_u32 v{{[0-9]+}}, v[[OFF]], v{{[0-9]+}} gds
81define amdgpu_kernel void @atomic_umax_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
82  %val = atomicrmw umax ptr addrspace(2) %gds, i32 5 acq_rel
83  store i32 %val, ptr addrspace(1) %out
84  ret void
85}
86
87; FUNC-LABEL: {{^}}atomic_imin_ret_gds:
88; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
89; GCN-DAG: s_movk_i32 m0, 0x1000
90; GCN: ds_min_rtn_i32 v{{[0-9]+}}, v[[OFF]], v{{[0-9]+}} gds
91define amdgpu_kernel void @atomic_imin_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
92  %val = atomicrmw min ptr addrspace(2) %gds, i32 5 acq_rel
93  store i32 %val, ptr addrspace(1) %out
94  ret void
95}
96
97; FUNC-LABEL: {{^}}atomic_imax_ret_gds:
98; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
99; GCN-DAG: s_movk_i32 m0, 0x1000
100; GCN: ds_max_rtn_i32 v{{[0-9]+}}, v[[OFF]], v{{[0-9]+}} gds
101define amdgpu_kernel void @atomic_imax_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
102  %val = atomicrmw max ptr addrspace(2) %gds, i32 5 acq_rel
103  store i32 %val, ptr addrspace(1) %out
104  ret void
105}
106
107; FUNC-LABEL: {{^}}atomic_xchg_ret_gds:
108; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
109; GCN-DAG: s_movk_i32 m0, 0x1000
110; GCN: ds_wrxchg_rtn_b32 v{{[0-9]+}}, v[[OFF]], v{{[0-9]+}} gds
111define amdgpu_kernel void @atomic_xchg_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
112  %val = atomicrmw xchg ptr addrspace(2) %gds, i32 5 acq_rel
113  store i32 %val, ptr addrspace(1) %out
114  ret void
115}
116
117; FUNC-LABEL: {{^}}atomic_cmpxchg_ret_gds:
118; GCN-DAG: v_mov_b32_e32 v[[OFF:[0-9]+]], s
119; GCN-DAG: s_movk_i32 m0, 0x1000
120; GCN: ds_cmpst_rtn_b32 v{{[0-9]+}}, v[[OFF:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} gds
121define amdgpu_kernel void @atomic_cmpxchg_ret_gds(ptr addrspace(1) %out, ptr addrspace(2) %gds) #1 {
122  %val = cmpxchg ptr addrspace(2) %gds, i32 0, i32 1 acquire acquire
123  %x = extractvalue { i32, i1 } %val, 0
124  store i32 %x, ptr addrspace(1) %out
125  ret void
126}
127
128attributes #0 = { nounwind "amdgpu-gds-size"="128" }
129attributes #1 = { nounwind "amdgpu-gds-size"="4096" }
130