1; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX10 2 3declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) 4declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg) 5 6; Check that this constant is not folded into the v_fmaak_f32 instruction. 7; GFX10-LABEL: _amdgpu_ps_main: 8; GFX10: v_mov_b32_e32 v1, 0x40490fdb 9; GFX10: v_fmaak_f32 v1, v0, v1, 0xbfc90fdb 10define amdgpu_ps void @_amdgpu_ps_main(float %arg) { 11bb: 12 %i = fmul reassoc nnan nsz arcp contract afn float %arg, 0x400921FB60000000 13 %i1 = fadd reassoc nnan nsz arcp contract afn float %i, 0xBFF921FB60000000 14 %i2 = fmul reassoc nnan nsz arcp contract afn float %i1, %arg 15 br label %bb3 16 17bb3: 18 br label %bb4 19 20bb4: 21 %i5 = fadd reassoc nnan nsz arcp contract afn float 0x400921FB60000000, %i2 22 br label %bb6 23 24bb6: 25 %i7 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %i5, float 0.000000e+00) 26 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> zeroinitializer, <2 x half> %i7, i1 false, i1 false) 27 ret void 28} 29