1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4; optnone disables AMDGPUAnnotateUniformValues, so no branch is known 5; to be uniform during instruction selection. The custom selection for 6; brcond was not checking if the branch was uniform, relying on the 7; selection pattern to check that. That would fail, so then the branch 8; would fail to select. 9 10; GCN-LABEL: {{^}}copytoreg_divergent_brcond: 11; GCN: s_branch 12 13; GCN-DAG: v_cmp_lt_i32 14; GCN-DAG: s_cmp_gt_i32 15; GCN: s_and_b64 16; GCN: s_mov_b64 exec 17 18; GCN: s_or_b64 exec, exec 19; GCN: {{[s|v]}}_cmp_eq_u32 20; GCN: s_cbranch_execz 21; GCN-NEXT: s_branch 22define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 { 23bb: 24 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 25 %tmp3 = zext i32 %tmp to i64 26 %tmp5 = add i64 %tmp3, undef 27 %tmp6 = trunc i64 %tmp5 to i32 28 %tmp7 = mul nsw i32 %tmp6, %arg2 29 br label %bb8 30 31bb8.loopexit: ; preds = %bb14 32 br label %bb8 33 34bb8: ; preds = %bb8.loopexit, %bb 35 br label %bb9 36 37bb9: ; preds = %bb14, %bb8 38 %tmp10 = icmp slt i32 %tmp7, %arg1 39 %tmp11 = icmp sgt i32 %arg, 0 40 %tmp12 = and i1 %tmp10, %tmp11 41 br i1 %tmp12, label %bb13, label %bb14 42 43bb13: ; preds = %bb9 44 store volatile i32 0, ptr addrspace(1) undef, align 4 45 br label %bb14 46 47bb14: ; preds = %bb13, %bb9 48 %tmp15 = icmp eq i32 %arg2, 1 49 br i1 %tmp15, label %bb8.loopexit, label %bb9 50} 51 52declare i32 @llvm.amdgcn.workitem.id.x() #1 53 54attributes #0 = { nounwind optnone noinline } 55attributes #1 = { nounwind readnone speculatable } 56