1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=amdgcn-amd-amdhsa -o - %s | FileCheck %s 3 4; The OR instruction should not be eliminated by the "OR Combine" DAG optimization. 5define protected amdgpu_kernel void @_Z11test_kernelPii(ptr addrspace(1) nocapture %Ad.coerce, i32 %s) local_unnamed_addr #5 { 6; CHECK-LABEL: _Z11test_kernelPii: 7; CHECK: ; %bb.0: ; %entry 8; CHECK-NEXT: s_load_dword s0, s[8:9], 0x2 9; CHECK-NEXT: s_waitcnt lgkmcnt(0) 10; CHECK-NEXT: s_cmp_lg_u32 s0, 3 11; CHECK-NEXT: s_cbranch_scc1 .LBB0_2 12; CHECK-NEXT: ; %bb.1: ; %if.then 13; CHECK-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0 14; CHECK-NEXT: s_and_b32 s4, s0, 0xffff 15; CHECK-NEXT: s_mov_b32 s1, 0 16; CHECK-NEXT: s_mul_i32 s6, s4, 0xaaab 17; CHECK-NEXT: s_lshl_b64 s[4:5], s[0:1], 2 18; CHECK-NEXT: s_lshr_b32 s1, s6, 19 19; CHECK-NEXT: s_mul_i32 s1, s1, 12 20; CHECK-NEXT: s_sub_i32 s6, s0, s1 21; CHECK-NEXT: s_and_b32 s7, s6, 0xffff 22; CHECK-NEXT: s_waitcnt lgkmcnt(0) 23; CHECK-NEXT: s_add_u32 s0, s2, s4 24; CHECK-NEXT: s_addc_u32 s1, s3, s5 25; CHECK-NEXT: s_bfe_u32 s2, s6, 0xd0003 26; CHECK-NEXT: s_add_i32 s2, s2, s7 27; CHECK-NEXT: s_or_b32 s2, s2, 0xc0 28; CHECK-NEXT: v_mov_b32_e32 v0, s0 29; CHECK-NEXT: v_mov_b32_e32 v1, s1 30; CHECK-NEXT: v_mov_b32_e32 v2, s2 31; CHECK-NEXT: flat_store_dword v[0:1], v2 32; CHECK-NEXT: .LBB0_2: ; %if.end 33; CHECK-NEXT: s_endpgm 34entry: 35 %cmp = icmp eq i32 %s, 3 36 br i1 %cmp, label %if.then, label %if.end 37 38if.then: ; preds = %entry 39 %rem.lhs.trunc = trunc i32 %s to i16 40 %rem4 = urem i16 %rem.lhs.trunc, 12 41 %rem.zext = zext i16 %rem4 to i32 42 %idxprom = zext i32 %s to i64 43 %arrayidx3 = getelementptr inbounds i32, ptr addrspace(1) %Ad.coerce, i64 %idxprom 44 %div = lshr i32 %rem.zext, 3 45 %or = or i32 %rem.zext, 192 46 %add = add nuw nsw i32 %or, %div 47 store i32 %add, ptr addrspace(1) %arrayidx3, align 4 48 br label %if.end 49 50if.end: ; preds = %if.then, %entry 51 ret void 52} 53