xref: /llvm-project/llvm/test/CodeGen/AMDGPU/cluster_stores.ll (revision 6548b6354d1d990e1c98736f5e7c3de876bedc8e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX9 %s
3; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t
4; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX10 %s
5; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t
6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX11 %s
7; RUN: FileCheck --enable-var-scope --check-prefixes=DBG,DBG11 %s < %t
8; REQUIRES: asserts
9
10; FIXME: Verifier error with xnack enabled.
11
12; DBG-LABEL: cluster_load_cluster_store:
13
14; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)
15; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)
16; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)
17; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)
18; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)
19
20; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
21; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
22; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
23
24; DBG11: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]])
25; DBG11: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]])
26; DBG11: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]])
27
28; DBG-NOT: Cluster ld/st
29
30define amdgpu_kernel void @cluster_load_cluster_store(ptr noalias %lb, ptr noalias %sb) {
31; GFX9-LABEL: cluster_load_cluster_store:
32; GFX9:       ; %bb.0: ; %bb
33; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
34; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
35; GFX9-NEXT:    v_mov_b32_e32 v0, s0
36; GFX9-NEXT:    v_mov_b32_e32 v1, s1
37; GFX9-NEXT:    flat_load_dword v2, v[0:1]
38; GFX9-NEXT:    flat_load_dword v3, v[0:1] offset:8
39; GFX9-NEXT:    flat_load_dword v4, v[0:1] offset:16
40; GFX9-NEXT:    flat_load_dword v5, v[0:1] offset:24
41; GFX9-NEXT:    v_mov_b32_e32 v0, s2
42; GFX9-NEXT:    v_mov_b32_e32 v1, s3
43; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
44; GFX9-NEXT:    flat_store_dword v[0:1], v2
45; GFX9-NEXT:    flat_store_dword v[0:1], v3 offset:8
46; GFX9-NEXT:    flat_store_dword v[0:1], v4 offset:16
47; GFX9-NEXT:    flat_store_dword v[0:1], v5 offset:24
48; GFX9-NEXT:    s_endpgm
49;
50; GFX10-LABEL: cluster_load_cluster_store:
51; GFX10:       ; %bb.0: ; %bb
52; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
53; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
54; GFX10-NEXT:    s_add_u32 s4, s0, 8
55; GFX10-NEXT:    s_addc_u32 s5, s1, 0
56; GFX10-NEXT:    s_add_u32 s6, s0, 16
57; GFX10-NEXT:    v_mov_b32_e32 v0, s0
58; GFX10-NEXT:    s_addc_u32 s7, s1, 0
59; GFX10-NEXT:    v_mov_b32_e32 v1, s1
60; GFX10-NEXT:    s_add_u32 s0, s0, 24
61; GFX10-NEXT:    v_mov_b32_e32 v2, s4
62; GFX10-NEXT:    s_addc_u32 s1, s1, 0
63; GFX10-NEXT:    v_mov_b32_e32 v3, s5
64; GFX10-NEXT:    v_mov_b32_e32 v4, s6
65; GFX10-NEXT:    v_mov_b32_e32 v5, s7
66; GFX10-NEXT:    v_mov_b32_e32 v7, s1
67; GFX10-NEXT:    v_mov_b32_e32 v6, s0
68; GFX10-NEXT:    s_clause 0x3
69; GFX10-NEXT:    flat_load_dword v8, v[0:1]
70; GFX10-NEXT:    flat_load_dword v9, v[2:3]
71; GFX10-NEXT:    flat_load_dword v10, v[4:5]
72; GFX10-NEXT:    flat_load_dword v11, v[6:7]
73; GFX10-NEXT:    s_add_u32 s0, s2, 8
74; GFX10-NEXT:    s_addc_u32 s1, s3, 0
75; GFX10-NEXT:    v_mov_b32_e32 v0, s2
76; GFX10-NEXT:    v_mov_b32_e32 v3, s1
77; GFX10-NEXT:    v_mov_b32_e32 v2, s0
78; GFX10-NEXT:    s_add_u32 s0, s2, 16
79; GFX10-NEXT:    s_addc_u32 s1, s3, 0
80; GFX10-NEXT:    v_mov_b32_e32 v1, s3
81; GFX10-NEXT:    s_add_u32 s2, s2, 24
82; GFX10-NEXT:    s_addc_u32 s3, s3, 0
83; GFX10-NEXT:    v_mov_b32_e32 v5, s1
84; GFX10-NEXT:    v_mov_b32_e32 v4, s0
85; GFX10-NEXT:    v_mov_b32_e32 v7, s3
86; GFX10-NEXT:    v_mov_b32_e32 v6, s2
87; GFX10-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
88; GFX10-NEXT:    flat_store_dword v[0:1], v8
89; GFX10-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(3)
90; GFX10-NEXT:    flat_store_dword v[2:3], v9
91; GFX10-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(3)
92; GFX10-NEXT:    flat_store_dword v[4:5], v10
93; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
94; GFX10-NEXT:    flat_store_dword v[6:7], v11
95; GFX10-NEXT:    s_endpgm
96;
97; GFX11-LABEL: cluster_load_cluster_store:
98; GFX11:       ; %bb.0: ; %bb
99; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
100; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
101; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
102; GFX11-NEXT:    s_clause 0x3
103; GFX11-NEXT:    flat_load_b32 v2, v[0:1]
104; GFX11-NEXT:    flat_load_b32 v3, v[0:1] offset:8
105; GFX11-NEXT:    flat_load_b32 v4, v[0:1] offset:16
106; GFX11-NEXT:    flat_load_b32 v5, v[0:1] offset:24
107; GFX11-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
108; GFX11-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
109; GFX11-NEXT:    flat_store_b32 v[0:1], v2
110; GFX11-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(3)
111; GFX11-NEXT:    flat_store_b32 v[0:1], v3 offset:8
112; GFX11-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(3)
113; GFX11-NEXT:    flat_store_b32 v[0:1], v4 offset:16
114; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
115; GFX11-NEXT:    flat_store_b32 v[0:1], v5 offset:24
116; GFX11-NEXT:    s_endpgm
117bb:
118  %ld0 = load i32, ptr %lb
119  %la1 = getelementptr inbounds i32, ptr %lb, i32 2
120  %ld1 = load i32, ptr %la1
121  %la2 = getelementptr inbounds i32, ptr %lb, i32 4
122  %ld2 = load i32, ptr %la2
123  %la3 = getelementptr inbounds i32, ptr %lb, i32 6
124  %ld3 = load i32, ptr %la3
125
126  store i32 %ld0, ptr %sb
127  %sa1 = getelementptr inbounds i32, ptr %sb, i32 2
128  store i32 %ld1, ptr %sa1
129  %sa2 = getelementptr inbounds i32, ptr %sb, i32 4
130  store i32 %ld2, ptr %sa2
131  %sa3 = getelementptr inbounds i32, ptr %sb, i32 6
132  store i32 %ld3, ptr %sa3
133
134  ret void
135}
136
137; DBG-LABEL: cluster_load_valu_cluster_store:
138
139; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)
140; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)
141; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)
142; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)
143; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)
144
145; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
146; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
147; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
148
149; DBG11: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]])
150; DBG11: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]])
151; DBG11: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]])
152
153; DBG-NOT: Cluster ld/st
154
155define amdgpu_kernel void @cluster_load_valu_cluster_store(ptr noalias %lb, ptr noalias %sb) {
156; GFX9-LABEL: cluster_load_valu_cluster_store:
157; GFX9:       ; %bb.0: ; %bb
158; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
159; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
160; GFX9-NEXT:    v_mov_b32_e32 v0, s0
161; GFX9-NEXT:    v_mov_b32_e32 v1, s1
162; GFX9-NEXT:    flat_load_dword v2, v[0:1]
163; GFX9-NEXT:    flat_load_dword v3, v[0:1] offset:8
164; GFX9-NEXT:    flat_load_dword v4, v[0:1] offset:16
165; GFX9-NEXT:    flat_load_dword v5, v[0:1] offset:24
166; GFX9-NEXT:    v_mov_b32_e32 v0, s2
167; GFX9-NEXT:    v_mov_b32_e32 v1, s3
168; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
169; GFX9-NEXT:    flat_store_dword v[0:1], v2
170; GFX9-NEXT:    v_add_u32_e32 v2, 1, v3
171; GFX9-NEXT:    flat_store_dword v[0:1], v4 offset:16
172; GFX9-NEXT:    flat_store_dword v[0:1], v2 offset:8
173; GFX9-NEXT:    flat_store_dword v[0:1], v5 offset:24
174; GFX9-NEXT:    s_endpgm
175;
176; GFX10-LABEL: cluster_load_valu_cluster_store:
177; GFX10:       ; %bb.0: ; %bb
178; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
179; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
180; GFX10-NEXT:    s_add_u32 s4, s0, 8
181; GFX10-NEXT:    s_addc_u32 s5, s1, 0
182; GFX10-NEXT:    v_mov_b32_e32 v2, s4
183; GFX10-NEXT:    s_add_u32 s6, s0, 16
184; GFX10-NEXT:    v_mov_b32_e32 v3, s5
185; GFX10-NEXT:    v_mov_b32_e32 v0, s0
186; GFX10-NEXT:    s_addc_u32 s7, s1, 0
187; GFX10-NEXT:    v_mov_b32_e32 v1, s1
188; GFX10-NEXT:    s_add_u32 s0, s0, 24
189; GFX10-NEXT:    s_addc_u32 s1, s1, 0
190; GFX10-NEXT:    v_mov_b32_e32 v4, s6
191; GFX10-NEXT:    v_mov_b32_e32 v5, s7
192; GFX10-NEXT:    flat_load_dword v6, v[2:3]
193; GFX10-NEXT:    v_mov_b32_e32 v3, s1
194; GFX10-NEXT:    v_mov_b32_e32 v2, s0
195; GFX10-NEXT:    s_clause 0x2
196; GFX10-NEXT:    flat_load_dword v8, v[0:1]
197; GFX10-NEXT:    flat_load_dword v9, v[4:5]
198; GFX10-NEXT:    flat_load_dword v10, v[2:3]
199; GFX10-NEXT:    s_add_u32 s0, s2, 8
200; GFX10-NEXT:    s_addc_u32 s1, s3, 0
201; GFX10-NEXT:    s_add_u32 s4, s2, 16
202; GFX10-NEXT:    v_mov_b32_e32 v3, s1
203; GFX10-NEXT:    s_addc_u32 s5, s3, 0
204; GFX10-NEXT:    v_mov_b32_e32 v0, s2
205; GFX10-NEXT:    v_mov_b32_e32 v2, s0
206; GFX10-NEXT:    s_add_u32 s0, s2, 24
207; GFX10-NEXT:    v_mov_b32_e32 v1, s3
208; GFX10-NEXT:    v_mov_b32_e32 v4, s4
209; GFX10-NEXT:    s_addc_u32 s1, s3, 0
210; GFX10-NEXT:    v_mov_b32_e32 v5, s5
211; GFX10-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
212; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v6
213; GFX10-NEXT:    v_mov_b32_e32 v7, s1
214; GFX10-NEXT:    v_mov_b32_e32 v6, s0
215; GFX10-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(2)
216; GFX10-NEXT:    flat_store_dword v[0:1], v8
217; GFX10-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(2)
218; GFX10-NEXT:    flat_store_dword v[4:5], v9
219; GFX10-NEXT:    flat_store_dword v[2:3], v11
220; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
221; GFX10-NEXT:    flat_store_dword v[6:7], v10
222; GFX10-NEXT:    s_endpgm
223;
224; GFX11-LABEL: cluster_load_valu_cluster_store:
225; GFX11:       ; %bb.0: ; %bb
226; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
227; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
228; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
229; GFX11-NEXT:    s_clause 0x3
230; GFX11-NEXT:    flat_load_b32 v2, v[0:1] offset:8
231; GFX11-NEXT:    flat_load_b32 v3, v[0:1]
232; GFX11-NEXT:    flat_load_b32 v4, v[0:1] offset:16
233; GFX11-NEXT:    flat_load_b32 v5, v[0:1] offset:24
234; GFX11-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
235; GFX11-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
236; GFX11-NEXT:    v_add_nc_u32_e32 v2, 1, v2
237; GFX11-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(2)
238; GFX11-NEXT:    s_clause 0x1
239; GFX11-NEXT:    flat_store_b32 v[0:1], v3
240; GFX11-NEXT:    flat_store_b32 v[0:1], v2 offset:8
241; GFX11-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(3)
242; GFX11-NEXT:    flat_store_b32 v[0:1], v4 offset:16
243; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
244; GFX11-NEXT:    flat_store_b32 v[0:1], v5 offset:24
245; GFX11-NEXT:    s_endpgm
246bb:
247  %ld0 = load i32, ptr %lb
248  %la1 = getelementptr inbounds i32, ptr %lb, i32 2
249  %ld1 = load i32, ptr %la1
250  %la2 = getelementptr inbounds i32, ptr %lb, i32 4
251  %ld2 = load i32, ptr %la2
252  %la3 = getelementptr inbounds i32, ptr %lb, i32 6
253  %ld3 = load i32, ptr %la3
254
255  store i32 %ld0, ptr %sb
256  %sa1 = getelementptr inbounds i32, ptr %sb, i32 2
257  %add = add i32 %ld1, 1
258  store i32 %add, ptr %sa1
259  %sa2 = getelementptr inbounds i32, ptr %sb, i32 4
260  store i32 %ld2, ptr %sa2
261  %sa3 = getelementptr inbounds i32, ptr %sb, i32 6
262  store i32 %ld3, ptr %sa3
263
264  ret void
265}
266
267; Cluster loads from the same texture with different coordinates
268; DBG-LABEL: cluster_image_load:
269; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)
270; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)
271; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
272; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_LOAD
273; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_LOAD
274define amdgpu_ps void @cluster_image_load(<8 x i32> inreg %src, <8 x i32> inreg %dst, i32 %x, i32 %y) {
275; GFX9-LABEL: cluster_image_load:
276; GFX9:       ; %bb.0: ; %entry
277; GFX9-NEXT:    v_add_u32_e32 v2, 1, v0
278; GFX9-NEXT:    v_add_u32_e32 v3, 1, v1
279; GFX9-NEXT:    v_add_u32_e32 v6, 2, v0
280; GFX9-NEXT:    v_add_u32_e32 v7, 2, v1
281; GFX9-NEXT:    image_load v[2:5], v[2:3], s[0:7] dmask:0xf unorm
282; GFX9-NEXT:    image_load v[6:9], v[6:7], s[0:7] dmask:0xf unorm
283; GFX9-NEXT:    s_waitcnt vmcnt(0)
284; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
285; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
286; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
287; GFX9-NEXT:    v_add_f32_e32 v2, v2, v6
288; GFX9-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf unorm
289; GFX9-NEXT:    s_endpgm
290;
291; GFX10-LABEL: cluster_image_load:
292; GFX10:       ; %bb.0: ; %entry
293; GFX10-NEXT:    v_add_nc_u32_e32 v10, 1, v0
294; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v1
295; GFX10-NEXT:    v_add_nc_u32_e32 v12, 2, v0
296; GFX10-NEXT:    v_add_nc_u32_e32 v13, 2, v1
297; GFX10-NEXT:    s_clause 0x1
298; GFX10-NEXT:    image_load v[2:5], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
299; GFX10-NEXT:    image_load v[6:9], v[12:13], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
300; GFX10-NEXT:    s_waitcnt vmcnt(0)
301; GFX10-NEXT:    v_add_f32_e32 v5, v5, v9
302; GFX10-NEXT:    v_add_f32_e32 v4, v4, v8
303; GFX10-NEXT:    v_add_f32_e32 v3, v3, v7
304; GFX10-NEXT:    v_add_f32_e32 v2, v2, v6
305; GFX10-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
306; GFX10-NEXT:    s_endpgm
307;
308; GFX11-LABEL: cluster_image_load:
309; GFX11:       ; %bb.0: ; %entry
310; GFX11-NEXT:    v_add_nc_u32_e32 v2, 1, v0
311; GFX11-NEXT:    v_add_nc_u32_e32 v3, 1, v1
312; GFX11-NEXT:    v_add_nc_u32_e32 v6, 2, v0
313; GFX11-NEXT:    v_add_nc_u32_e32 v7, 2, v1
314; GFX11-NEXT:    s_clause 0x1
315; GFX11-NEXT:    image_load v[2:5], v[2:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
316; GFX11-NEXT:    image_load v[6:9], v[6:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
317; GFX11-NEXT:    s_waitcnt vmcnt(0)
318; GFX11-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v5, v5, v9
319; GFX11-NEXT:    v_dual_add_f32 v4, v4, v8 :: v_dual_add_f32 v3, v3, v7
320; GFX11-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
321; GFX11-NEXT:    s_endpgm
322entry:
323  %x1 = add i32 %x, 1
324  %y1 = add i32 %y, 1
325  %val1 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x1, i32 %y1, <8 x i32> %src, i32 0, i32 0)
326  %x2 = add i32 %x, 2
327  %y2 = add i32 %y, 2
328  %val2 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x2, i32 %y2, <8 x i32> %src, i32 0, i32 0)
329  %val = fadd fast <4 x float> %val1, %val2
330  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
331  ret void
332}
333
334; Don't cluster loads from different textures
335; DBG-LABEL: no_cluster_image_load:
336; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)
337; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)
338; DBG-NOT: {{^}}Cluster ld/st
339define amdgpu_ps void @no_cluster_image_load(<8 x i32> inreg %src1, <8 x i32> inreg %src2, <8 x i32> inreg %dst, i32 %x, i32 %y) {
340; GFX9-LABEL: no_cluster_image_load:
341; GFX9:       ; %bb.0: ; %entry
342; GFX9-NEXT:    v_mov_b32_e32 v2, 0
343; GFX9-NEXT:    image_load_mip v[3:6], v[0:2], s[0:7] dmask:0xf unorm
344; GFX9-NEXT:    image_load_mip v[7:10], v[0:2], s[8:15] dmask:0xf unorm
345; GFX9-NEXT:    s_waitcnt vmcnt(0)
346; GFX9-NEXT:    v_add_f32_e32 v6, v6, v10
347; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
348; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
349; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
350; GFX9-NEXT:    image_store v[3:6], v[0:1], s[16:23] dmask:0xf unorm
351; GFX9-NEXT:    s_endpgm
352;
353; GFX10-LABEL: no_cluster_image_load:
354; GFX10:       ; %bb.0: ; %entry
355; GFX10-NEXT:    v_mov_b32_e32 v10, 0
356; GFX10-NEXT:    image_load_mip v[2:5], [v0, v1, v10], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
357; GFX10-NEXT:    image_load_mip v[6:9], [v0, v1, v10], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
358; GFX10-NEXT:    s_waitcnt vmcnt(0)
359; GFX10-NEXT:    v_add_f32_e32 v5, v5, v9
360; GFX10-NEXT:    v_add_f32_e32 v4, v4, v8
361; GFX10-NEXT:    v_add_f32_e32 v3, v3, v7
362; GFX10-NEXT:    v_add_f32_e32 v2, v2, v6
363; GFX10-NEXT:    image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
364; GFX10-NEXT:    s_endpgm
365;
366; GFX11-LABEL: no_cluster_image_load:
367; GFX11:       ; %bb.0: ; %entry
368; GFX11-NEXT:    v_mov_b32_e32 v6, 0
369; GFX11-NEXT:    image_load_mip v[2:5], [v0, v1, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
370; GFX11-NEXT:    image_load_mip v[6:9], [v0, v1, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
371; GFX11-NEXT:    s_waitcnt vmcnt(0)
372; GFX11-NEXT:    v_dual_add_f32 v5, v5, v9 :: v_dual_add_f32 v4, v4, v8
373; GFX11-NEXT:    v_dual_add_f32 v3, v3, v7 :: v_dual_add_f32 v2, v2, v6
374; GFX11-NEXT:    image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
375; GFX11-NEXT:    s_endpgm
376entry:
377  %val1 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src1, i32 0, i32 0)
378  %val2 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src2, i32 0, i32 0)
379  %val = fadd fast <4 x float> %val1, %val2
380  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
381  ret void
382}
383
384; Cluster loads from the same texture and sampler with different coordinates
385; DBG-LABEL: cluster_image_sample:
386; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)
387; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)
388; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
389; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_SAMPLE
390; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_SAMPLE
391define amdgpu_ps void @cluster_image_sample(<8 x i32> inreg %src, <4 x i32> inreg %smp, <8 x i32> inreg %dst, i32 %x, i32 %y) {
392; GFX9-LABEL: cluster_image_sample:
393; GFX9:       ; %bb.0: ; %entry
394; GFX9-NEXT:    v_cvt_f32_i32_e32 v8, v0
395; GFX9-NEXT:    v_cvt_f32_i32_e32 v9, v1
396; GFX9-NEXT:    v_mov_b32_e32 v4, 0
397; GFX9-NEXT:    v_mov_b32_e32 v5, v4
398; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v8
399; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v9
400; GFX9-NEXT:    v_mov_b32_e32 v6, v4
401; GFX9-NEXT:    v_mov_b32_e32 v7, v4
402; GFX9-NEXT:    v_add_f32_e32 v8, 2.0, v8
403; GFX9-NEXT:    v_add_f32_e32 v9, 2.0, v9
404; GFX9-NEXT:    v_mov_b32_e32 v10, 1.0
405; GFX9-NEXT:    v_mov_b32_e32 v11, v10
406; GFX9-NEXT:    v_mov_b32_e32 v12, v10
407; GFX9-NEXT:    v_mov_b32_e32 v13, v10
408; GFX9-NEXT:    image_sample_d v[2:5], v[2:7], s[0:7], s[8:11] dmask:0xf
409; GFX9-NEXT:    image_sample_d v[6:9], v[8:13], s[0:7], s[8:11] dmask:0xf
410; GFX9-NEXT:    s_waitcnt vmcnt(0)
411; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
412; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
413; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
414; GFX9-NEXT:    v_add_f32_e32 v2, v2, v6
415; GFX9-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf unorm
416; GFX9-NEXT:    s_endpgm
417;
418; GFX10-LABEL: cluster_image_sample:
419; GFX10:       ; %bb.0: ; %entry
420; GFX10-NEXT:    v_cvt_f32_i32_e32 v8, v0
421; GFX10-NEXT:    v_cvt_f32_i32_e32 v9, v1
422; GFX10-NEXT:    v_mov_b32_e32 v4, 0
423; GFX10-NEXT:    v_mov_b32_e32 v10, 1.0
424; GFX10-NEXT:    v_add_f32_e32 v2, 1.0, v8
425; GFX10-NEXT:    v_add_f32_e32 v3, 1.0, v9
426; GFX10-NEXT:    v_mov_b32_e32 v5, v4
427; GFX10-NEXT:    v_mov_b32_e32 v6, v4
428; GFX10-NEXT:    v_mov_b32_e32 v7, v4
429; GFX10-NEXT:    v_add_f32_e32 v8, 2.0, v8
430; GFX10-NEXT:    v_add_f32_e32 v9, 2.0, v9
431; GFX10-NEXT:    v_mov_b32_e32 v11, v10
432; GFX10-NEXT:    v_mov_b32_e32 v12, v10
433; GFX10-NEXT:    v_mov_b32_e32 v13, v10
434; GFX10-NEXT:    s_clause 0x1
435; GFX10-NEXT:    image_sample_d v[14:17], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
436; GFX10-NEXT:    image_sample_d v[18:21], v[8:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
437; GFX10-NEXT:    s_waitcnt vmcnt(0)
438; GFX10-NEXT:    v_add_f32_e32 v5, v17, v21
439; GFX10-NEXT:    v_add_f32_e32 v4, v16, v20
440; GFX10-NEXT:    v_add_f32_e32 v3, v15, v19
441; GFX10-NEXT:    v_add_f32_e32 v2, v14, v18
442; GFX10-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
443; GFX10-NEXT:    s_endpgm
444;
445; GFX11-LABEL: cluster_image_sample:
446; GFX11:       ; %bb.0: ; %entry
447; GFX11-NEXT:    v_cvt_f32_i32_e32 v4, v0
448; GFX11-NEXT:    v_cvt_f32_i32_e32 v5, v1
449; GFX11-NEXT:    v_mov_b32_e32 v2, 0
450; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
451; GFX11-NEXT:    v_dual_mov_b32 v6, 1.0 :: v_dual_add_f32 v11, 2.0, v5
452; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v5 :: v_dual_add_f32 v8, 1.0, v4
453; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
454; GFX11-NEXT:    v_dual_mov_b32 v3, v2 :: v_dual_add_f32 v10, 2.0, v4
455; GFX11-NEXT:    v_mov_b32_e32 v7, v6
456; GFX11-NEXT:    s_clause 0x1
457; GFX11-NEXT:    image_sample_d v[2:5], [v8, v9, v2, v2, v[2:3]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
458; GFX11-NEXT:    image_sample_d v[6:9], [v10, v11, v6, v6, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
459; GFX11-NEXT:    s_waitcnt vmcnt(0)
460; GFX11-NEXT:    v_dual_add_f32 v5, v5, v9 :: v_dual_add_f32 v4, v4, v8
461; GFX11-NEXT:    v_dual_add_f32 v3, v3, v7 :: v_dual_add_f32 v2, v2, v6
462; GFX11-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
463; GFX11-NEXT:    s_endpgm
464entry:
465  %s = sitofp i32 %x to float
466  %t = sitofp i32 %y to float
467  %s1 = fadd float %s, 1.0
468  %t1 = fadd float %t, 1.0
469  %val1 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s1, float %t1, float 0.0, float 0.0, float 0.0, float 0.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
470  %s2 = fadd float %s, 2.0
471  %t2 = fadd float %t, 2.0
472  %val2 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s2, float %t2, float 1.0, float 1.0, float 1.0, float 1.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
473  %val = fadd fast <4 x float> %val1, %val2
474  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
475  ret void
476}
477
478declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
479declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
480declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
481declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
482