xref: /llvm-project/llvm/test/CodeGen/AMDGPU/call-constexpr.ll (revision b1bcb7ca460fcd317bbc8309e14c8761bf8394e0)
1; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3; GCN-LABEL: {{^}}test_bitcast_return_type_noinline:
4; GCN: s_getpc_b64
5; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ret_i32_noinline@rel32@lo+4
6; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ret_i32_noinline@rel32@hi+12
7; GCN: s_swappc_b64
8define amdgpu_kernel void @test_bitcast_return_type_noinline() #0 {
9  %val = call float @ret_i32_noinline()
10  %op = fadd float %val, 1.0
11  store volatile float %op, ptr addrspace(1) undef
12  ret void
13}
14
15; GCN-LABEL: {{^}}test_bitcast_return_type_alwaysinline:
16; GCN: s_swappc_b64
17define amdgpu_kernel void @test_bitcast_return_type_alwaysinline() #0 {
18  %val = call float @ret_i32_alwaysinline()
19  %op = fadd float %val, 1.0
20  store volatile float %op, ptr addrspace(1) undef
21  ret void
22}
23
24; GCN-LABEL: {{^}}test_bitcast_argument_type:
25; GCN: s_getpc_b64
26; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@lo+4
27; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@hi+12
28; GCN: s_swappc_b64
29define amdgpu_kernel void @test_bitcast_argument_type() #0 {
30  %val = call i32 @ident_i32(float 2.0)
31  %op = add i32 %val, 1
32  store volatile i32 %op, ptr addrspace(1) undef
33  ret void
34}
35
36; GCN-LABEL: {{^}}test_bitcast_argument_and_return_types:
37; GCN: s_getpc_b64
38; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@lo+4
39; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@hi+12
40; GCN: s_swappc_b64
41define amdgpu_kernel void @test_bitcast_argument_and_return_types() #0 {
42  %val = call float @ident_i32(float 2.0)
43  %op = fadd float %val, 1.0
44  store volatile float %op, ptr addrspace(1) undef
45  ret void
46}
47
48; GCN-LABEL: {{^}}use_workitem_id_x:
49; GCN: s_waitcnt
50; GCN-NEXT: v_and_b32_e32 [[TMP:v[0-9]+]], 0x3ff, v31
51; GCN-NEXT: v_add_i32_e32 v0, vcc, [[TMP]], v0
52; GCN-NEXT: s_setpc_b64
53define hidden i32 @use_workitem_id_x(i32 %arg0) #3 {
54  %id = call i32 @llvm.amdgcn.workitem.id.x()
55  %op = add i32 %id, %arg0
56  ret i32 %op
57}
58
59; GCN-LABEL: {{^}}test_bitcast_use_workitem_id_x:
60; GCN: v_mov_b32_e32 v31, v0
61; GCN: s_getpc_b64
62; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, use_workitem_id_x@rel32@lo+4
63; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, use_workitem_id_x@rel32@hi+12
64; GCN: v_mov_b32_e32 v0, 9
65; GCN: s_swappc_b64
66; GCN: v_add_f32_e32
67define amdgpu_kernel void @test_bitcast_use_workitem_id_x() #3 {
68  %val = call float @use_workitem_id_x(i32 9)
69  %op = fadd float %val, 1.0
70  store volatile float %op, ptr addrspace(1) undef
71  ret void
72}
73
74; GCN-LABEL: {{^}}test_invoke:
75; GCN: s_getpc_b64
76; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@lo+4
77; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@hi+12
78; GCN: s_swappc_b64
79@_ZTIi = external global ptr
80declare i32 @__gxx_personality_v0(...)
81define amdgpu_kernel void @test_invoke() #0 personality ptr @__gxx_personality_v0 {
82  %val = invoke float @ident_i32(float 2.0)
83          to label %continue unwind label %broken
84
85broken:
86  landingpad { ptr, i32 } catch ptr @_ZTIi
87  ret void
88
89continue:
90  %op = fadd float %val, 1.0
91  store volatile float %op, ptr addrspace(1) undef
92  ret void
93}
94
95; Callees appears last in source file to test that we still lower their
96; arguments before we lower any calls to them.
97
98define hidden i32 @ret_i32_noinline() #0 {
99  ret i32 4
100}
101
102define hidden i32 @ret_i32_alwaysinline() #1 {
103  ret i32 4
104}
105
106define hidden i32 @ident_i32(i32 %i) #0 {
107  ret i32 %i
108}
109
110declare i32 @llvm.amdgcn.workitem.id.x() #2
111
112attributes #0 = { nounwind noinline }
113attributes #1 = { alwaysinline nounwind }
114attributes #2 = { nounwind readnone speculatable }
115attributes #3 = { nounwind noinline "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
116