1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 2; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck %s 3 4define amdgpu_cs <2 x i32> @f() { 5; CHECK-LABEL: f: 6; CHECK: ; %bb.0: ; %bb 7; CHECK-NEXT: s_mov_b32 s4, 0 8; CHECK-NEXT: s_mov_b32 s5, s4 9; CHECK-NEXT: s_mov_b32 s6, s4 10; CHECK-NEXT: s_mov_b32 s7, s4 11; CHECK-NEXT: s_mov_b32 s0, s4 12; CHECK-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 13; CHECK-NEXT: s_mov_b32 s1, s4 14; CHECK-NEXT: s_waitcnt vmcnt(0) 15; CHECK-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[0:1], v[0:1] 16; CHECK-NEXT: v_mov_b32_e32 v1, s4 17; CHECK-NEXT: s_mov_b32 s1, 0 18; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo 19; CHECK-NEXT: v_readfirstlane_b32 s0, v0 20; CHECK-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 21; CHECK-NEXT: ; return to shader part epilog 22bb: 23 %i = call <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32> zeroinitializer, i32 0, i32 0, i32 0) 24 %i1 = bitcast <2 x i32> %i to i64 25 %i2 = insertelement <3 x i64> zeroinitializer, i64 %i1, i64 2 26 %i3 = icmp ne <3 x i64> %i2, zeroinitializer 27 %i4 = zext <3 x i1> %i3 to <3 x i64> 28 %i5 = bitcast <3 x i64> %i4 to <6 x i32> 29 %i6 = shufflevector <6 x i32> %i5, <6 x i32> zeroinitializer, <2 x i32> <i32 4, i32 5> 30 call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %i6, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0) 31 ret <2 x i32> %i6 32} 33 34declare <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32>, i32, i32, i32 immarg) 35declare void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32 immarg) 36