1; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s 2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s 3 4; The buffer_loads and buffer_stores all access the same location. Check they do 5; not get reordered by the scheduler. 6 7; GCN-LABEL: {{^}}test1: 8; GCN: buffer_store_dword 9; GCN: buffer_load_dword 10; GCN: buffer_store_dword 11define amdgpu_cs void @test1(<4 x i32> inreg %buf, i32 %off) { 12.entry: 13 call void @llvm.amdgcn.raw.buffer.store.i32(i32 0, <4 x i32> %buf, i32 8, i32 0, i32 0) 14 %val = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %buf, i32 %off, i32 0, i32 0) 15 call void @llvm.amdgcn.raw.buffer.store.i32(i32 %val, <4 x i32> %buf, i32 0, i32 0, i32 0) 16 ret void 17} 18 19; GCN-LABEL: {{^}}test1_ptrs: 20; GCN: buffer_store_dword 21; GCN: buffer_load_dword 22; GCN: buffer_store_dword 23define amdgpu_cs void @test1_ptrs(ptr addrspace(8) inreg %buf, i32 %off) { 24.entry: 25 call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 0, ptr addrspace(8) %buf, i32 8, i32 0, i32 0) 26 %val = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) %buf, i32 %off, i32 0, i32 0) 27 call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 %val, ptr addrspace(8) %buf, i32 0, i32 0, i32 0) 28 ret void 29} 30 31;; In the future, the stores should be reorderable because they'd be known to be 32;; at distinct offsets. 33; GCN-LABEL: {{^}}test1_ptrs_reorderable: 34; GCN: buffer_store_dword 35; GCN: buffer_load_dword 36; GCN: buffer_store_dword 37define amdgpu_cs void @test1_ptrs_reorderable(ptr addrspace(8) inreg %buf, i32 %off) { 38.entry: 39 %shifted.off = shl i32 %off, 4 40 call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 0, ptr addrspace(8) %buf, i32 8, i32 0, i32 0) 41 %val = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) %buf, i32 %shifted.off, i32 0, i32 0) 42 call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 %val, ptr addrspace(8) %buf, i32 0, i32 0, i32 0) 43 ret void 44} 45 46 47declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #2 48 49declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32) #3 50 51declare i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) nocapture, i32, i32, i32) #4 52 53declare void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32, ptr addrspace(8) nocapture, i32, i32, i32) #5 54 55attributes #2 = { nounwind readonly } 56attributes #3 = { nounwind writeonly } 57attributes #4 = { nounwind memory(argmem: read) } 58attributes #5 = { nounwind memory(argmem: write) } 59