1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals 2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck %s 3 4%0 = type { ptr, ptr } 5 6define internal fastcc i1 @widget(ptr %arg) { 7; CHECK-LABEL: define {{[^@]+}}@widget 8; CHECK-SAME: (ptr [[ARG:%.*]]) #[[ATTR0:[0-9]+]] { 9; CHECK-NEXT: bb: 10; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds [[TMP0:%.*]], ptr [[ARG]], i64 0, i32 1 11; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 12; CHECK-NEXT: [[TMP2:%.*]] = call fastcc double @baz(ptr [[TMP1]]) 13; CHECK-NEXT: ret i1 false 14; 15bb: 16 %tmp = getelementptr inbounds %0, ptr %arg, i64 0, i32 1 17 %tmp1 = load ptr, ptr %tmp, align 8 18 %tmp2 = call fastcc double @baz(ptr %tmp1) 19 ret i1 false 20} 21 22define internal fastcc double @baz(ptr %arg) { 23; CHECK-LABEL: define {{[^@]+}}@baz 24; CHECK-SAME: (ptr [[ARG:%.*]]) #[[ATTR0]] { 25; CHECK-NEXT: bb: 26; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARG]], align 8 27; CHECK-NEXT: [[TMP2:%.*]] = tail call double [[TMP1]]() 28; CHECK-NEXT: br label [[BB3:%.*]] 29; CHECK: bb3: 30; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[TMP0:%.*]], ptr [[ARG]], i64 0, i32 1 31; CHECK-NEXT: br label [[BB5:%.*]] 32; CHECK: bb5: 33; CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP4]], align 8 34; CHECK-NEXT: [[TMP7:%.*]] = call fastcc i1 @widget(ptr [[TMP6]]) 35; CHECK-NEXT: br label [[BB5]] 36; 37bb: 38 %tmp1 = load ptr, ptr %arg, align 8 39 %tmp2 = tail call double %tmp1() 40 br label %bb3 41 42bb3: ; preds = %bb 43 %tmp4 = getelementptr inbounds %0, ptr %arg, i64 0, i32 1 44 br label %bb5 45 46bb5: ; preds = %bb5, %bb3 47 %tmp6 = load ptr, ptr %tmp4, align 8 48 %tmp7 = call fastcc i1 @widget(ptr %tmp6) 49 br label %bb5 50} 51 52define amdgpu_kernel void @entry() { 53; CHECK-LABEL: define {{[^@]+}}@entry 54; CHECK-SAME: () #[[ATTR1:[0-9]+]] { 55; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [[TMP0:%.*]], align 8, addrspace(5) 56; CHECK-NEXT: [[CAST:%.*]] = addrspacecast ptr addrspace(5) [[ALLOCA]] to ptr 57; CHECK-NEXT: [[ARST:%.*]] = call double @baz(ptr [[CAST]]) 58; CHECK-NEXT: ret void 59; 60 %alloca = alloca %0, align 8, addrspace(5) 61 %cast = addrspacecast ptr addrspace(5) %alloca to ptr 62 %arst = call double @baz(ptr %cast) 63 ret void 64} 65;. 66; CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="false" } 67; CHECK: attributes #[[ATTR1]] = { "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" } 68;. 69