1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -mtriple=amdgcn-- -mcpu=gfx908 -passes="amdgpu-atomic-optimizer,verify<domtree>" %s -S -o - | FileCheck %s 3 4; Check we're properly adding an edge from ComputeEnd to the "End" block added by 5; SplitBlockAndInsertIfThen 6; 7; If the edge is not added, domtree verification will fail. 8 9declare i32 @quux() 10 11define amdgpu_kernel void @ham(ptr addrspace(4) %arg) { 12; CHECK-LABEL: define amdgpu_kernel void @ham( 13; CHECK-SAME: ptr addrspace(4) [[ARG:%.*]]) #[[ATTR0:[0-9]+]] { 14; CHECK-NEXT: bb: 15; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @quux() 16; CHECK-NEXT: [[ICMP:%.*]] = icmp eq i32 [[CALL]], 0 17; CHECK-NEXT: br i1 [[ICMP]], label [[BB1:%.*]], label [[BB3:%.*]] 18; CHECK: bb1: 19; CHECK-NEXT: [[CALL2:%.*]] = tail call i32 @quux() 20; CHECK-NEXT: br label [[BB3]] 21; CHECK: bb3: 22; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[CALL2]], [[BB1]] ], [ [[CALL]], [[BB:%.*]] ] 23; CHECK-NEXT: br label [[BB4:%.*]] 24; CHECK: bb4: 25; CHECK-NEXT: [[CALL5:%.*]] = tail call i32 @quux() 26; CHECK-NEXT: [[ICMP6:%.*]] = icmp eq i32 [[CALL5]], 0 27; CHECK-NEXT: br i1 [[ICMP6]], label [[BB8:%.*]], label [[BB7:%.*]] 28; CHECK: bb7: 29; CHECK-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[ARG]], align 8 30; CHECK-NEXT: [[ADDRSPACECAST:%.*]] = addrspacecast ptr [[LOAD]] to ptr addrspace(1) 31; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) 32; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32 33; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32 34; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32 35; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0) 36; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]]) 37; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) 38; CHECK-NEXT: br label [[COMPUTELOOP:%.*]] 39; CHECK: 7: 40; CHECK-NEXT: [[TMP8:%.*]] = atomicrmw add ptr addrspace(1) [[ADDRSPACECAST]], i32 [[TMP13:%.*]] syncscope("agent-one-as") monotonic, align 4 41; CHECK-NEXT: br label [[TMP9:%.*]] 42; CHECK: 9: 43; CHECK-NEXT: br label [[BB8]] 44; CHECK: bb8: 45; CHECK-NEXT: br label [[BB4]] 46; CHECK: ComputeLoop: 47; CHECK-NEXT: [[ACCUMULATOR:%.*]] = phi i32 [ 0, [[BB7]] ], [ [[TMP13]], [[COMPUTELOOP]] ] 48; CHECK-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP6]], [[BB7]] ], [ [[TMP16:%.*]], [[COMPUTELOOP]] ] 49; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) 50; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP10]] to i32 51; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[PHI]], i32 [[TMP11]]) 52; CHECK-NEXT: [[TMP13]] = add i32 [[ACCUMULATOR]], [[TMP12]] 53; CHECK-NEXT: [[TMP14:%.*]] = shl i64 1, [[TMP10]] 54; CHECK-NEXT: [[TMP15:%.*]] = xor i64 [[TMP14]], -1 55; CHECK-NEXT: [[TMP16]] = and i64 [[ACTIVEBITS]], [[TMP15]] 56; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[TMP16]], 0 57; CHECK-NEXT: br i1 [[TMP17]], label [[COMPUTEEND:%.*]], label [[COMPUTELOOP]] 58; CHECK: ComputeEnd: 59; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP5]], 0 60; CHECK-NEXT: br i1 [[TMP18]], label [[TMP7:%.*]], label [[TMP9]] 61; 62bb: 63 %call = tail call i32 @quux() 64 %icmp = icmp eq i32 %call, 0 65 br i1 %icmp, label %bb1, label %bb3 66 67bb1: ; preds = %bb 68 %call2 = tail call i32 @quux() 69 br label %bb3 70 71bb3: ; preds = %bb1, %bb 72 %phi = phi i32 [ %call2, %bb1 ], [ %call, %bb ] 73 br label %bb4 74 75bb4: ; preds = %bb8, %bb3 76 %call5 = tail call i32 @quux() 77 %icmp6 = icmp eq i32 %call5, 0 78 br i1 %icmp6, label %bb8, label %bb7 79 80bb7: ; preds = %bb4 81 %load = load ptr, ptr addrspace(4) %arg, align 8 82 %addrspacecast = addrspacecast ptr %load to ptr addrspace(1) 83 %atomicrmw = atomicrmw add ptr addrspace(1) %addrspacecast, i32 %phi syncscope("agent-one-as") monotonic, align 4 84 br label %bb8 85 86bb8: ; preds = %bb7, %bb4 87 br label %bb4 88} 89