1; RUN: llc -verify-machineinstrs -mtriple=amdgcn -mcpu=tahiti -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s 2; RUN: llc -verify-machineinstrs -mtriple=amdgcn -mcpu=tahiti -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s 3 4declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 5declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1 6declare void @llvm.amdgcn.s.barrier() #2 7 8; The required pointer calculations for the alloca'd actually requires 9; an add and won't be folded into the addressing, which fails with a 10; 64-bit pointer add. This should work since private pointers should 11; be 32-bits. 12 13; SI-LABEL: {{^}}test_private_array_ptr_calc: 14 15; SI-ALLOCA: buffer_load_dword [[LOAD_A:v[0-9]+]] 16; SI-ALLOCA: buffer_load_dword [[LOAD_B:v[0-9]+]] 17 18; SI-ALLOCA: v_lshlrev_b32_e32 [[SIZE_SCALE:v[0-9]+]], 2, [[LOAD_A]] 19 20; SI-ALLOCA: v_mov_b32_e32 [[PTRREG:v[0-9]+]], [[SIZE_SCALE]] 21; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], 0 offen offset:64 22; SI-ALLOCA: s_barrier 23; SI-ALLOCA: buffer_load_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], 0 offen offset:64 24; 25; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this 26; alloca to a vector. It currently fails because it does not know how 27; to interpret: 28; getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 1, i32 %b 29 30; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 64 31; SI-PROMOTE: ds_write_b32 [[PTRREG]] 32define amdgpu_kernel void @test_private_array_ptr_calc(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) #0 { 33 %alloca = alloca [16 x i32], align 16, addrspace(5) 34 %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0); 35 %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo) 36 %a_ptr = getelementptr inbounds i32, ptr addrspace(1) %inA, i32 %tid 37 %b_ptr = getelementptr inbounds i32, ptr addrspace(1) %inB, i32 %tid 38 %a = load i32, ptr addrspace(1) %a_ptr, !range !0, !noundef !{} 39 %b = load i32, ptr addrspace(1) %b_ptr, !range !0, !noundef !{} 40 %result = add i32 %a, %b 41 %alloca_ptr = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 1, i32 %b 42 store i32 %result, ptr addrspace(5) %alloca_ptr, align 4 43 ; Dummy call 44 call void @llvm.amdgcn.s.barrier() 45 %reload = load i32, ptr addrspace(5) %alloca_ptr, align 4, !range !0, !noundef !{} 46 %out_ptr = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %tid 47 store i32 %reload, ptr addrspace(1) %out_ptr, align 4 48 ret void 49} 50 51attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="1,256" } 52attributes #1 = { nounwind readnone } 53attributes #2 = { nounwind convergent } 54 55!0 = !{i32 0, i32 65536 } 56