xref: /llvm-project/llvm/test/CodeGen/AMDGPU/anyext.ll (revision 6548b6354d1d990e1c98736f5e7c3de876bedc8e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
5
6declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
7declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
8
9define amdgpu_kernel void @anyext_i1_i32(ptr addrspace(1) %out, i32 %cond) #0 {
10; GCN-LABEL: anyext_i1_i32:
11; GCN:       ; %bb.0: ; %entry
12; GCN-NEXT:    s_load_dword s6, s[4:5], 0xb
13; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
14; GCN-NEXT:    s_mov_b32 s3, 0xf000
15; GCN-NEXT:    s_mov_b32 s2, -1
16; GCN-NEXT:    s_waitcnt lgkmcnt(0)
17; GCN-NEXT:    s_cmp_lg_u32 s6, 0
18; GCN-NEXT:    s_cselect_b64 s[4:5], -1, 0
19; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
20; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
21; GCN-NEXT:    s_endpgm
22;
23; GFX8-LABEL: anyext_i1_i32:
24; GFX8:       ; %bb.0: ; %entry
25; GFX8-NEXT:    s_load_dword s6, s[4:5], 0x2c
26; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
27; GFX8-NEXT:    s_mov_b32 s3, 0xf000
28; GFX8-NEXT:    s_mov_b32 s2, -1
29; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
30; GFX8-NEXT:    s_cmp_eq_u32 s6, 0
31; GFX8-NEXT:    s_cselect_b64 s[4:5], -1, 0
32; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
33; GFX8-NEXT:    v_not_b32_e32 v0, v0
34; GFX8-NEXT:    v_and_b32_e32 v0, 1, v0
35; GFX8-NEXT:    buffer_store_dword v0, off, s[0:3], 0
36; GFX8-NEXT:    s_endpgm
37;
38; GFX9-LABEL: anyext_i1_i32:
39; GFX9:       ; %bb.0: ; %entry
40; GFX9-NEXT:    s_load_dword s6, s[4:5], 0x2c
41; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
42; GFX9-NEXT:    s_mov_b32 s3, 0xf000
43; GFX9-NEXT:    s_mov_b32 s2, -1
44; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
45; GFX9-NEXT:    s_cmp_eq_u32 s6, 0
46; GFX9-NEXT:    s_cselect_b64 s[4:5], -1, 0
47; GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
48; GFX9-NEXT:    v_not_b32_e32 v0, v0
49; GFX9-NEXT:    v_and_b32_e32 v0, 1, v0
50; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
51; GFX9-NEXT:    s_endpgm
52entry:
53  %tmp = icmp eq i32 %cond, 0
54  %tmp1 = zext i1 %tmp to i8
55  %tmp2 = xor i8 %tmp1, -1
56  %tmp3 = and i8 %tmp2, 1
57  %tmp4 = zext i8 %tmp3 to i32
58  store i32 %tmp4, ptr addrspace(1) %out
59  ret void
60}
61
62define amdgpu_kernel void @s_anyext_i16_i32(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) #0 {
63; GCN-LABEL: s_anyext_i16_i32:
64; GCN:       ; %bb.0: ; %entry
65; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
66; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
67; GCN-NEXT:    s_mov_b32 s11, 0xf000
68; GCN-NEXT:    s_mov_b32 s14, 0
69; GCN-NEXT:    s_mov_b32 s15, s11
70; GCN-NEXT:    s_waitcnt lgkmcnt(0)
71; GCN-NEXT:    s_mov_b64 s[12:13], s[2:3]
72; GCN-NEXT:    v_lshlrev_b32_e32 v2, 1, v0
73; GCN-NEXT:    v_mov_b32_e32 v3, 0
74; GCN-NEXT:    v_lshlrev_b32_e32 v0, 1, v1
75; GCN-NEXT:    s_mov_b64 s[6:7], s[14:15]
76; GCN-NEXT:    v_mov_b32_e32 v1, v3
77; GCN-NEXT:    buffer_load_ushort v2, v[2:3], s[12:15], 0 addr64
78; GCN-NEXT:    buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64
79; GCN-NEXT:    s_mov_b32 s10, -1
80; GCN-NEXT:    s_mov_b32 s8, s0
81; GCN-NEXT:    s_mov_b32 s9, s1
82; GCN-NEXT:    s_waitcnt vmcnt(0)
83; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
84; GCN-NEXT:    v_not_b32_e32 v0, v0
85; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
86; GCN-NEXT:    buffer_store_dword v0, off, s[8:11], 0
87; GCN-NEXT:    s_endpgm
88;
89; GFX8-LABEL: s_anyext_i16_i32:
90; GFX8:       ; %bb.0: ; %entry
91; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
92; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
93; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
94; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
95; GFX8-NEXT:    v_mov_b32_e32 v3, s3
96; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s2, v0
97; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
98; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v1
99; GFX8-NEXT:    v_mov_b32_e32 v1, s5
100; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v0
101; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
102; GFX8-NEXT:    flat_load_ushort v2, v[2:3]
103; GFX8-NEXT:    flat_load_ushort v0, v[0:1]
104; GFX8-NEXT:    s_mov_b32 s3, 0xf000
105; GFX8-NEXT:    s_mov_b32 s2, -1
106; GFX8-NEXT:    s_waitcnt vmcnt(0)
107; GFX8-NEXT:    v_add_u16_e32 v0, v2, v0
108; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
109; GFX8-NEXT:    v_and_b32_e32 v0, 1, v0
110; GFX8-NEXT:    v_and_b32_e32 v0, 0xffff, v0
111; GFX8-NEXT:    buffer_store_dword v0, off, s[0:3], 0
112; GFX8-NEXT:    s_endpgm
113;
114; GFX9-LABEL: s_anyext_i16_i32:
115; GFX9:       ; %bb.0: ; %entry
116; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
117; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
118; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
119; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
120; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
121; GFX9-NEXT:    global_load_ushort v2, v0, s[2:3]
122; GFX9-NEXT:    global_load_ushort v3, v1, s[6:7]
123; GFX9-NEXT:    s_mov_b32 s3, 0xf000
124; GFX9-NEXT:    s_mov_b32 s2, -1
125; GFX9-NEXT:    s_waitcnt vmcnt(0)
126; GFX9-NEXT:    v_add_u16_e32 v0, v2, v3
127; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
128; GFX9-NEXT:    v_and_b32_e32 v0, 1, v0
129; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
130; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
131; GFX9-NEXT:    s_endpgm
132entry:
133  %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
134  %tid.y = call i32 @llvm.amdgcn.workitem.id.y()
135  %a.ptr = getelementptr i16, ptr addrspace(1) %a, i32 %tid.x
136  %b.ptr = getelementptr i16, ptr addrspace(1) %b, i32 %tid.y
137  %a.l = load i16, ptr addrspace(1) %a.ptr
138  %b.l = load i16, ptr addrspace(1) %b.ptr
139  %tmp = add i16 %a.l, %b.l
140  %tmp1 = trunc i16 %tmp to i8
141  %tmp2 = xor i8 %tmp1, -1
142  %tmp3 = and i8 %tmp2, 1
143  %tmp4 = zext i8 %tmp3 to i32
144  store i32 %tmp4, ptr addrspace(1) %out
145  ret void
146}
147
148define amdgpu_kernel void @anyext_v2i16_to_v2i32() #0 {
149; GCN-LABEL: anyext_v2i16_to_v2i32:
150; GCN:       ; %bb.0: ; %bb
151; GCN-NEXT:    s_mov_b32 s3, 0xf000
152; GCN-NEXT:    s_mov_b32 s2, -1
153; GCN-NEXT:    buffer_load_ushort v0, off, s[0:3], 0
154; GCN-NEXT:    s_waitcnt vmcnt(0)
155; GCN-NEXT:    v_and_b32_e32 v0, 0x8001, v0
156; GCN-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
157; GCN-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
158; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
159; GCN-NEXT:    buffer_store_byte v0, off, s[0:3], 0
160; GCN-NEXT:    s_endpgm
161;
162; GFX8-LABEL: anyext_v2i16_to_v2i32:
163; GFX8:       ; %bb.0: ; %bb
164; GFX8-NEXT:    s_mov_b32 s3, 0xf000
165; GFX8-NEXT:    s_mov_b32 s2, -1
166; GFX8-NEXT:    buffer_load_ushort v0, off, s[0:3], 0
167; GFX8-NEXT:    v_mov_b32_e32 v1, 0x8001
168; GFX8-NEXT:    s_waitcnt vmcnt(0)
169; GFX8-NEXT:    v_and_b32_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
170; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
171; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
172; GFX8-NEXT:    buffer_store_byte v0, off, s[0:3], 0
173; GFX8-NEXT:    s_endpgm
174;
175; GFX9-LABEL: anyext_v2i16_to_v2i32:
176; GFX9:       ; %bb.0: ; %bb
177; GFX9-NEXT:    global_load_short_d16_hi v0, v[0:1], off
178; GFX9-NEXT:    v_mov_b32_e32 v1, 0xffff
179; GFX9-NEXT:    s_mov_b32 s3, 0xf000
180; GFX9-NEXT:    s_mov_b32 s2, -1
181; GFX9-NEXT:    s_waitcnt vmcnt(0)
182; GFX9-NEXT:    v_and_b32_e32 v0, 0x80018001, v0
183; GFX9-NEXT:    v_bfi_b32 v0, v1, 0, v0
184; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
185; GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
186; GFX9-NEXT:    buffer_store_byte v0, off, s[0:3], 0
187; GFX9-NEXT:    s_endpgm
188bb:
189  %tmp = load i16, ptr addrspace(1) undef, align 2
190  %tmp2 = insertelement <2 x i16> undef, i16 %tmp, i32 1
191  %tmp4 = and <2 x i16> %tmp2, <i16 -32767, i16 -32767>
192  %tmp5 = zext <2 x i16> %tmp4 to <2 x i32>
193  %tmp6 = shl nuw <2 x i32> %tmp5, <i32 16, i32 16>
194  %tmp7 = or <2 x i32> zeroinitializer, %tmp6
195  %tmp8 = bitcast <2 x i32> %tmp7 to <2 x float>
196  %tmp10 = fcmp oeq <2 x float> %tmp8, zeroinitializer
197  %tmp11 = zext <2 x i1> %tmp10 to <2 x i8>
198  %tmp12 = extractelement <2 x i8> %tmp11, i32 1
199  store i8 %tmp12, ptr addrspace(1) undef, align 1
200  ret void
201}
202
203attributes #0 = { nounwind }
204