1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals 2; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefixes=CHECK,AKF_CHECK %s 3; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-attributor < %s | FileCheck -check-prefixes=CHECK,ATTRIBUTOR_CHECK %s 4 5declare i32 @llvm.r600.read.tgid.x() #0 6declare i32 @llvm.r600.read.tgid.y() #0 7declare i32 @llvm.r600.read.tgid.z() #0 8 9declare i32 @llvm.r600.read.tidig.x() #0 10declare i32 @llvm.r600.read.tidig.y() #0 11declare i32 @llvm.r600.read.tidig.z() #0 12 13declare i32 @llvm.r600.read.local.size.x() #0 14declare i32 @llvm.r600.read.local.size.y() #0 15declare i32 @llvm.r600.read.local.size.z() #0 16 17define amdgpu_kernel void @use_tgid_x(ptr addrspace(1) %ptr) #1 { 18; CHECK-LABEL: define {{[^@]+}}@use_tgid_x 19; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1:[0-9]+]] { 20; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.x() 21; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 22; CHECK-NEXT: ret void 23; 24 %val = call i32 @llvm.r600.read.tgid.x() 25 store i32 %val, ptr addrspace(1) %ptr 26 ret void 27} 28 29define amdgpu_kernel void @use_tgid_y(ptr addrspace(1) %ptr) #1 { 30; AKF_CHECK-LABEL: define {{[^@]+}}@use_tgid_y 31; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 32; AKF_CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.y() 33; AKF_CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 34; AKF_CHECK-NEXT: ret void 35; 36; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_tgid_y 37; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2:[0-9]+]] { 38; ATTRIBUTOR_CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.y() 39; ATTRIBUTOR_CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 40; ATTRIBUTOR_CHECK-NEXT: ret void 41; 42 %val = call i32 @llvm.r600.read.tgid.y() 43 store i32 %val, ptr addrspace(1) %ptr 44 ret void 45} 46 47define amdgpu_kernel void @multi_use_tgid_y(ptr addrspace(1) %ptr) #1 { 48; AKF_CHECK-LABEL: define {{[^@]+}}@multi_use_tgid_y 49; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 50; AKF_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.y() 51; AKF_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 52; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y() 53; AKF_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 54; AKF_CHECK-NEXT: ret void 55; 56; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@multi_use_tgid_y 57; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2]] { 58; ATTRIBUTOR_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.y() 59; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 60; ATTRIBUTOR_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y() 61; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 62; ATTRIBUTOR_CHECK-NEXT: ret void 63; 64 %val0 = call i32 @llvm.r600.read.tgid.y() 65 store volatile i32 %val0, ptr addrspace(1) %ptr 66 %val1 = call i32 @llvm.r600.read.tgid.y() 67 store volatile i32 %val1, ptr addrspace(1) %ptr 68 ret void 69} 70 71define amdgpu_kernel void @use_tgid_x_y(ptr addrspace(1) %ptr) #1 { 72; AKF_CHECK-LABEL: define {{[^@]+}}@use_tgid_x_y 73; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 74; AKF_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x() 75; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y() 76; AKF_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 77; AKF_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 78; AKF_CHECK-NEXT: ret void 79; 80; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_tgid_x_y 81; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2]] { 82; ATTRIBUTOR_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x() 83; ATTRIBUTOR_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y() 84; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 85; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 86; ATTRIBUTOR_CHECK-NEXT: ret void 87; 88 %val0 = call i32 @llvm.r600.read.tgid.x() 89 %val1 = call i32 @llvm.r600.read.tgid.y() 90 store volatile i32 %val0, ptr addrspace(1) %ptr 91 store volatile i32 %val1, ptr addrspace(1) %ptr 92 ret void 93} 94 95define amdgpu_kernel void @use_tgid_z(ptr addrspace(1) %ptr) #1 { 96; AKF_CHECK-LABEL: define {{[^@]+}}@use_tgid_z 97; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 98; AKF_CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.z() 99; AKF_CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 100; AKF_CHECK-NEXT: ret void 101; 102; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_tgid_z 103; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3:[0-9]+]] { 104; ATTRIBUTOR_CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tgid.z() 105; ATTRIBUTOR_CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 106; ATTRIBUTOR_CHECK-NEXT: ret void 107; 108 %val = call i32 @llvm.r600.read.tgid.z() 109 store i32 %val, ptr addrspace(1) %ptr 110 ret void 111} 112 113define amdgpu_kernel void @use_tgid_x_z(ptr addrspace(1) %ptr) #1 { 114; AKF_CHECK-LABEL: define {{[^@]+}}@use_tgid_x_z 115; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 116; AKF_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x() 117; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.z() 118; AKF_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 119; AKF_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 120; AKF_CHECK-NEXT: ret void 121; 122; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_tgid_x_z 123; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3]] { 124; ATTRIBUTOR_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x() 125; ATTRIBUTOR_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.z() 126; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 127; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 128; ATTRIBUTOR_CHECK-NEXT: ret void 129; 130 %val0 = call i32 @llvm.r600.read.tgid.x() 131 %val1 = call i32 @llvm.r600.read.tgid.z() 132 store volatile i32 %val0, ptr addrspace(1) %ptr 133 store volatile i32 %val1, ptr addrspace(1) %ptr 134 ret void 135} 136 137define amdgpu_kernel void @use_tgid_y_z(ptr addrspace(1) %ptr) #1 { 138; AKF_CHECK-LABEL: define {{[^@]+}}@use_tgid_y_z 139; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 140; AKF_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.y() 141; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.z() 142; AKF_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 143; AKF_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 144; AKF_CHECK-NEXT: ret void 145; 146; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_tgid_y_z 147; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR4:[0-9]+]] { 148; ATTRIBUTOR_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.y() 149; ATTRIBUTOR_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.z() 150; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 151; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 152; ATTRIBUTOR_CHECK-NEXT: ret void 153; 154 %val0 = call i32 @llvm.r600.read.tgid.y() 155 %val1 = call i32 @llvm.r600.read.tgid.z() 156 store volatile i32 %val0, ptr addrspace(1) %ptr 157 store volatile i32 %val1, ptr addrspace(1) %ptr 158 ret void 159} 160 161define amdgpu_kernel void @use_tgid_x_y_z(ptr addrspace(1) %ptr) #1 { 162; AKF_CHECK-LABEL: define {{[^@]+}}@use_tgid_x_y_z 163; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 164; AKF_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x() 165; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y() 166; AKF_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tgid.z() 167; AKF_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 168; AKF_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 169; AKF_CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 170; AKF_CHECK-NEXT: ret void 171; 172; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_tgid_x_y_z 173; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR4]] { 174; ATTRIBUTOR_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tgid.x() 175; ATTRIBUTOR_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y() 176; ATTRIBUTOR_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tgid.z() 177; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 178; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 179; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 180; ATTRIBUTOR_CHECK-NEXT: ret void 181; 182 %val0 = call i32 @llvm.r600.read.tgid.x() 183 %val1 = call i32 @llvm.r600.read.tgid.y() 184 %val2 = call i32 @llvm.r600.read.tgid.z() 185 store volatile i32 %val0, ptr addrspace(1) %ptr 186 store volatile i32 %val1, ptr addrspace(1) %ptr 187 store volatile i32 %val2, ptr addrspace(1) %ptr 188 ret void 189} 190 191define amdgpu_kernel void @use_tidig_x(ptr addrspace(1) %ptr) #1 { 192; CHECK-LABEL: define {{[^@]+}}@use_tidig_x 193; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 194; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.x() 195; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 196; CHECK-NEXT: ret void 197; 198 %val = call i32 @llvm.r600.read.tidig.x() 199 store i32 %val, ptr addrspace(1) %ptr 200 ret void 201} 202 203define amdgpu_kernel void @use_tidig_y(ptr addrspace(1) %ptr) #1 { 204; AKF_CHECK-LABEL: define {{[^@]+}}@use_tidig_y 205; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 206; AKF_CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.y() 207; AKF_CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 208; AKF_CHECK-NEXT: ret void 209; 210; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_tidig_y 211; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR5:[0-9]+]] { 212; ATTRIBUTOR_CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.y() 213; ATTRIBUTOR_CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 214; ATTRIBUTOR_CHECK-NEXT: ret void 215; 216 %val = call i32 @llvm.r600.read.tidig.y() 217 store i32 %val, ptr addrspace(1) %ptr 218 ret void 219} 220 221define amdgpu_kernel void @use_tidig_z(ptr addrspace(1) %ptr) #1 { 222; AKF_CHECK-LABEL: define {{[^@]+}}@use_tidig_z 223; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 224; AKF_CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.z() 225; AKF_CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 226; AKF_CHECK-NEXT: ret void 227; 228; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_tidig_z 229; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR6:[0-9]+]] { 230; ATTRIBUTOR_CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.tidig.z() 231; ATTRIBUTOR_CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 232; ATTRIBUTOR_CHECK-NEXT: ret void 233; 234 %val = call i32 @llvm.r600.read.tidig.z() 235 store i32 %val, ptr addrspace(1) %ptr 236 ret void 237} 238 239define amdgpu_kernel void @use_tidig_x_tgid_x(ptr addrspace(1) %ptr) #1 { 240; CHECK-LABEL: define {{[^@]+}}@use_tidig_x_tgid_x 241; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 242; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x() 243; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.x() 244; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 245; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 246; CHECK-NEXT: ret void 247; 248 %val0 = call i32 @llvm.r600.read.tidig.x() 249 %val1 = call i32 @llvm.r600.read.tgid.x() 250 store volatile i32 %val0, ptr addrspace(1) %ptr 251 store volatile i32 %val1, ptr addrspace(1) %ptr 252 ret void 253} 254 255define amdgpu_kernel void @use_tidig_y_tgid_y(ptr addrspace(1) %ptr) #1 { 256; AKF_CHECK-LABEL: define {{[^@]+}}@use_tidig_y_tgid_y 257; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 258; AKF_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.y() 259; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y() 260; AKF_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 261; AKF_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 262; AKF_CHECK-NEXT: ret void 263; 264; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_tidig_y_tgid_y 265; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR7:[0-9]+]] { 266; ATTRIBUTOR_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.y() 267; ATTRIBUTOR_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y() 268; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 269; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 270; ATTRIBUTOR_CHECK-NEXT: ret void 271; 272 %val0 = call i32 @llvm.r600.read.tidig.y() 273 %val1 = call i32 @llvm.r600.read.tgid.y() 274 store volatile i32 %val0, ptr addrspace(1) %ptr 275 store volatile i32 %val1, ptr addrspace(1) %ptr 276 ret void 277} 278 279define amdgpu_kernel void @use_tidig_x_y_z(ptr addrspace(1) %ptr) #1 { 280; AKF_CHECK-LABEL: define {{[^@]+}}@use_tidig_x_y_z 281; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 282; AKF_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x() 283; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tidig.y() 284; AKF_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z() 285; AKF_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 286; AKF_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 287; AKF_CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 288; AKF_CHECK-NEXT: ret void 289; 290; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_tidig_x_y_z 291; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR8:[0-9]+]] { 292; ATTRIBUTOR_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x() 293; ATTRIBUTOR_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tidig.y() 294; ATTRIBUTOR_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z() 295; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 296; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 297; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 298; ATTRIBUTOR_CHECK-NEXT: ret void 299; 300 %val0 = call i32 @llvm.r600.read.tidig.x() 301 %val1 = call i32 @llvm.r600.read.tidig.y() 302 %val2 = call i32 @llvm.r600.read.tidig.z() 303 store volatile i32 %val0, ptr addrspace(1) %ptr 304 store volatile i32 %val1, ptr addrspace(1) %ptr 305 store volatile i32 %val2, ptr addrspace(1) %ptr 306 ret void 307} 308 309define amdgpu_kernel void @use_all_workitems(ptr addrspace(1) %ptr) #1 { 310; AKF_CHECK-LABEL: define {{[^@]+}}@use_all_workitems 311; AKF_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 312; AKF_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x() 313; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tidig.y() 314; AKF_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z() 315; AKF_CHECK-NEXT: [[VAL3:%.*]] = call i32 @llvm.r600.read.tgid.x() 316; AKF_CHECK-NEXT: [[VAL4:%.*]] = call i32 @llvm.r600.read.tgid.y() 317; AKF_CHECK-NEXT: [[VAL5:%.*]] = call i32 @llvm.r600.read.tgid.z() 318; AKF_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 319; AKF_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 320; AKF_CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 321; AKF_CHECK-NEXT: store volatile i32 [[VAL3]], ptr addrspace(1) [[PTR]], align 4 322; AKF_CHECK-NEXT: store volatile i32 [[VAL4]], ptr addrspace(1) [[PTR]], align 4 323; AKF_CHECK-NEXT: store volatile i32 [[VAL5]], ptr addrspace(1) [[PTR]], align 4 324; AKF_CHECK-NEXT: ret void 325; 326; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@use_all_workitems 327; ATTRIBUTOR_CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR9:[0-9]+]] { 328; ATTRIBUTOR_CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.r600.read.tidig.x() 329; ATTRIBUTOR_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tidig.y() 330; ATTRIBUTOR_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z() 331; ATTRIBUTOR_CHECK-NEXT: [[VAL3:%.*]] = call i32 @llvm.r600.read.tgid.x() 332; ATTRIBUTOR_CHECK-NEXT: [[VAL4:%.*]] = call i32 @llvm.r600.read.tgid.y() 333; ATTRIBUTOR_CHECK-NEXT: [[VAL5:%.*]] = call i32 @llvm.r600.read.tgid.z() 334; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 335; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 336; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 337; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL3]], ptr addrspace(1) [[PTR]], align 4 338; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL4]], ptr addrspace(1) [[PTR]], align 4 339; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL5]], ptr addrspace(1) [[PTR]], align 4 340; ATTRIBUTOR_CHECK-NEXT: ret void 341; 342 %val0 = call i32 @llvm.r600.read.tidig.x() 343 %val1 = call i32 @llvm.r600.read.tidig.y() 344 %val2 = call i32 @llvm.r600.read.tidig.z() 345 %val3 = call i32 @llvm.r600.read.tgid.x() 346 %val4 = call i32 @llvm.r600.read.tgid.y() 347 %val5 = call i32 @llvm.r600.read.tgid.z() 348 store volatile i32 %val0, ptr addrspace(1) %ptr 349 store volatile i32 %val1, ptr addrspace(1) %ptr 350 store volatile i32 %val2, ptr addrspace(1) %ptr 351 store volatile i32 %val3, ptr addrspace(1) %ptr 352 store volatile i32 %val4, ptr addrspace(1) %ptr 353 store volatile i32 %val5, ptr addrspace(1) %ptr 354 ret void 355} 356 357define amdgpu_kernel void @use_get_local_size_x(ptr addrspace(1) %ptr) #1 { 358; CHECK-LABEL: define {{[^@]+}}@use_get_local_size_x 359; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 360; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.local.size.x() 361; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 362; CHECK-NEXT: ret void 363; 364 %val = call i32 @llvm.r600.read.local.size.x() 365 store i32 %val, ptr addrspace(1) %ptr 366 ret void 367} 368 369define amdgpu_kernel void @use_get_local_size_y(ptr addrspace(1) %ptr) #1 { 370; CHECK-LABEL: define {{[^@]+}}@use_get_local_size_y 371; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 372; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.local.size.y() 373; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 374; CHECK-NEXT: ret void 375; 376 %val = call i32 @llvm.r600.read.local.size.y() 377 store i32 %val, ptr addrspace(1) %ptr 378 ret void 379} 380 381define amdgpu_kernel void @use_get_local_size_z(ptr addrspace(1) %ptr) #1 { 382; CHECK-LABEL: define {{[^@]+}}@use_get_local_size_z 383; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 384; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.r600.read.local.size.z() 385; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 386; CHECK-NEXT: ret void 387; 388 %val = call i32 @llvm.r600.read.local.size.z() 389 store i32 %val, ptr addrspace(1) %ptr 390 ret void 391} 392 393attributes #0 = { nounwind readnone } 394attributes #1 = { nounwind } 395 396;. 397; AKF_CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 398; AKF_CHECK: attributes #[[ATTR1]] = { nounwind } 399;. 400; ATTRIBUTOR_CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 401; ATTRIBUTOR_CHECK: attributes #[[ATTR1]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 402; ATTRIBUTOR_CHECK: attributes #[[ATTR2]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 403; ATTRIBUTOR_CHECK: attributes #[[ATTR3]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 404; ATTRIBUTOR_CHECK: attributes #[[ATTR4]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 405; ATTRIBUTOR_CHECK: attributes #[[ATTR5]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 406; ATTRIBUTOR_CHECK: attributes #[[ATTR6]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" } 407; ATTRIBUTOR_CHECK: attributes #[[ATTR7]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 408; ATTRIBUTOR_CHECK: attributes #[[ATTR8]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } 409; ATTRIBUTOR_CHECK: attributes #[[ATTR9]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } 410;. 411