1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals 2; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefixes=HSA,AKF_HSA %s 3; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -passes=amdgpu-attributor < %s | FileCheck -check-prefixes=HSA,ATTRIBUTOR_HSA %s 4 5target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" 6 7declare i32 @llvm.amdgcn.workgroup.id.x() #0 8declare i32 @llvm.amdgcn.workgroup.id.y() #0 9declare i32 @llvm.amdgcn.workgroup.id.z() #0 10 11declare i32 @llvm.amdgcn.workitem.id.x() #0 12declare i32 @llvm.amdgcn.workitem.id.y() #0 13declare i32 @llvm.amdgcn.workitem.id.z() #0 14 15declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #0 16declare ptr addrspace(4) @llvm.amdgcn.queue.ptr() #0 17declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #0 18declare ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0 19 20declare i1 @llvm.amdgcn.is.shared(ptr nocapture) #2 21declare i1 @llvm.amdgcn.is.private(ptr nocapture) #2 22 23define amdgpu_kernel void @use_tgid_x(ptr addrspace(1) %ptr) #1 { 24; HSA-LABEL: define {{[^@]+}}@use_tgid_x 25; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1:[0-9]+]] { 26; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 27; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 28; HSA-NEXT: ret void 29; 30 %val = call i32 @llvm.amdgcn.workgroup.id.x() 31 store i32 %val, ptr addrspace(1) %ptr 32 ret void 33} 34 35define amdgpu_kernel void @use_tgid_y(ptr addrspace(1) %ptr) #1 { 36; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_y 37; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 38; AKF_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 39; AKF_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 40; AKF_HSA-NEXT: ret void 41; 42; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_y 43; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2:[0-9]+]] { 44; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 45; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 46; ATTRIBUTOR_HSA-NEXT: ret void 47; 48 %val = call i32 @llvm.amdgcn.workgroup.id.y() 49 store i32 %val, ptr addrspace(1) %ptr 50 ret void 51} 52 53define amdgpu_kernel void @multi_use_tgid_y(ptr addrspace(1) %ptr) #1 { 54; AKF_HSA-LABEL: define {{[^@]+}}@multi_use_tgid_y 55; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 56; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 57; AKF_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 58; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 59; AKF_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 60; AKF_HSA-NEXT: ret void 61; 62; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@multi_use_tgid_y 63; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2]] { 64; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 65; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 66; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 67; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 68; ATTRIBUTOR_HSA-NEXT: ret void 69; 70 %val0 = call i32 @llvm.amdgcn.workgroup.id.y() 71 store volatile i32 %val0, ptr addrspace(1) %ptr 72 %val1 = call i32 @llvm.amdgcn.workgroup.id.y() 73 store volatile i32 %val1, ptr addrspace(1) %ptr 74 ret void 75} 76 77define amdgpu_kernel void @use_tgid_x_y(ptr addrspace(1) %ptr) #1 { 78; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_x_y 79; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 80; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 81; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 82; AKF_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 83; AKF_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 84; AKF_HSA-NEXT: ret void 85; 86; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_x_y 87; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR2]] { 88; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 89; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 90; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 91; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 92; ATTRIBUTOR_HSA-NEXT: ret void 93; 94 %val0 = call i32 @llvm.amdgcn.workgroup.id.x() 95 %val1 = call i32 @llvm.amdgcn.workgroup.id.y() 96 store volatile i32 %val0, ptr addrspace(1) %ptr 97 store volatile i32 %val1, ptr addrspace(1) %ptr 98 ret void 99} 100 101define amdgpu_kernel void @use_tgid_z(ptr addrspace(1) %ptr) #1 { 102; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_z 103; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 104; AKF_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 105; AKF_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 106; AKF_HSA-NEXT: ret void 107; 108; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_z 109; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3:[0-9]+]] { 110; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 111; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 112; ATTRIBUTOR_HSA-NEXT: ret void 113; 114 %val = call i32 @llvm.amdgcn.workgroup.id.z() 115 store i32 %val, ptr addrspace(1) %ptr 116 ret void 117} 118 119define amdgpu_kernel void @use_tgid_x_z(ptr addrspace(1) %ptr) #1 { 120; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_x_z 121; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 122; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 123; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 124; AKF_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 125; AKF_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 126; AKF_HSA-NEXT: ret void 127; 128; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_x_z 129; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3]] { 130; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 131; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 132; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 133; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 134; ATTRIBUTOR_HSA-NEXT: ret void 135; 136 %val0 = call i32 @llvm.amdgcn.workgroup.id.x() 137 %val1 = call i32 @llvm.amdgcn.workgroup.id.z() 138 store volatile i32 %val0, ptr addrspace(1) %ptr 139 store volatile i32 %val1, ptr addrspace(1) %ptr 140 ret void 141} 142 143define amdgpu_kernel void @use_tgid_y_z(ptr addrspace(1) %ptr) #1 { 144; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_y_z 145; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 146; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 147; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 148; AKF_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 149; AKF_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 150; AKF_HSA-NEXT: ret void 151; 152; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_y_z 153; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR4:[0-9]+]] { 154; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 155; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 156; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 157; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 158; ATTRIBUTOR_HSA-NEXT: ret void 159; 160 %val0 = call i32 @llvm.amdgcn.workgroup.id.y() 161 %val1 = call i32 @llvm.amdgcn.workgroup.id.z() 162 store volatile i32 %val0, ptr addrspace(1) %ptr 163 store volatile i32 %val1, ptr addrspace(1) %ptr 164 ret void 165} 166 167define amdgpu_kernel void @use_tgid_x_y_z(ptr addrspace(1) %ptr) #1 { 168; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_x_y_z 169; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 170; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 171; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 172; AKF_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 173; AKF_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 174; AKF_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 175; AKF_HSA-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 176; AKF_HSA-NEXT: ret void 177; 178; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_x_y_z 179; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR4]] { 180; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 181; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 182; ATTRIBUTOR_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 183; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 184; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 185; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 186; ATTRIBUTOR_HSA-NEXT: ret void 187; 188 %val0 = call i32 @llvm.amdgcn.workgroup.id.x() 189 %val1 = call i32 @llvm.amdgcn.workgroup.id.y() 190 %val2 = call i32 @llvm.amdgcn.workgroup.id.z() 191 store volatile i32 %val0, ptr addrspace(1) %ptr 192 store volatile i32 %val1, ptr addrspace(1) %ptr 193 store volatile i32 %val2, ptr addrspace(1) %ptr 194 ret void 195} 196 197define amdgpu_kernel void @use_tidig_x(ptr addrspace(1) %ptr) #1 { 198; HSA-LABEL: define {{[^@]+}}@use_tidig_x 199; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 200; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 201; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 202; HSA-NEXT: ret void 203; 204 %val = call i32 @llvm.amdgcn.workitem.id.x() 205 store i32 %val, ptr addrspace(1) %ptr 206 ret void 207} 208 209define amdgpu_kernel void @use_tidig_y(ptr addrspace(1) %ptr) #1 { 210; AKF_HSA-LABEL: define {{[^@]+}}@use_tidig_y 211; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 212; AKF_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 213; AKF_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 214; AKF_HSA-NEXT: ret void 215; 216; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tidig_y 217; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR5:[0-9]+]] { 218; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 219; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 220; ATTRIBUTOR_HSA-NEXT: ret void 221; 222 %val = call i32 @llvm.amdgcn.workitem.id.y() 223 store i32 %val, ptr addrspace(1) %ptr 224 ret void 225} 226 227define amdgpu_kernel void @use_tidig_z(ptr addrspace(1) %ptr) #1 { 228; AKF_HSA-LABEL: define {{[^@]+}}@use_tidig_z 229; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 230; AKF_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 231; AKF_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 232; AKF_HSA-NEXT: ret void 233; 234; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tidig_z 235; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR6:[0-9]+]] { 236; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 237; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 238; ATTRIBUTOR_HSA-NEXT: ret void 239; 240 %val = call i32 @llvm.amdgcn.workitem.id.z() 241 store i32 %val, ptr addrspace(1) %ptr 242 ret void 243} 244 245define amdgpu_kernel void @use_tidig_x_tgid_x(ptr addrspace(1) %ptr) #1 { 246; HSA-LABEL: define {{[^@]+}}@use_tidig_x_tgid_x 247; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 248; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 249; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 250; HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 251; HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 252; HSA-NEXT: ret void 253; 254 %val0 = call i32 @llvm.amdgcn.workitem.id.x() 255 %val1 = call i32 @llvm.amdgcn.workgroup.id.x() 256 store volatile i32 %val0, ptr addrspace(1) %ptr 257 store volatile i32 %val1, ptr addrspace(1) %ptr 258 ret void 259} 260 261define amdgpu_kernel void @use_tidig_y_tgid_y(ptr addrspace(1) %ptr) #1 { 262; AKF_HSA-LABEL: define {{[^@]+}}@use_tidig_y_tgid_y 263; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 264; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 265; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 266; AKF_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 267; AKF_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 268; AKF_HSA-NEXT: ret void 269; 270; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tidig_y_tgid_y 271; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR7:[0-9]+]] { 272; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 273; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 274; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 275; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 276; ATTRIBUTOR_HSA-NEXT: ret void 277; 278 %val0 = call i32 @llvm.amdgcn.workitem.id.y() 279 %val1 = call i32 @llvm.amdgcn.workgroup.id.y() 280 store volatile i32 %val0, ptr addrspace(1) %ptr 281 store volatile i32 %val1, ptr addrspace(1) %ptr 282 ret void 283} 284 285define amdgpu_kernel void @use_tidig_x_y_z(ptr addrspace(1) %ptr) #1 { 286; AKF_HSA-LABEL: define {{[^@]+}}@use_tidig_x_y_z 287; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 288; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 289; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 290; AKF_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 291; AKF_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 292; AKF_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 293; AKF_HSA-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 294; AKF_HSA-NEXT: ret void 295; 296; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tidig_x_y_z 297; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR8:[0-9]+]] { 298; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 299; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 300; ATTRIBUTOR_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 301; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 302; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 303; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 304; ATTRIBUTOR_HSA-NEXT: ret void 305; 306 %val0 = call i32 @llvm.amdgcn.workitem.id.x() 307 %val1 = call i32 @llvm.amdgcn.workitem.id.y() 308 %val2 = call i32 @llvm.amdgcn.workitem.id.z() 309 store volatile i32 %val0, ptr addrspace(1) %ptr 310 store volatile i32 %val1, ptr addrspace(1) %ptr 311 store volatile i32 %val2, ptr addrspace(1) %ptr 312 ret void 313} 314 315define amdgpu_kernel void @use_all_workitems(ptr addrspace(1) %ptr) #1 { 316; AKF_HSA-LABEL: define {{[^@]+}}@use_all_workitems 317; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 318; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 319; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 320; AKF_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 321; AKF_HSA-NEXT: [[VAL3:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 322; AKF_HSA-NEXT: [[VAL4:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 323; AKF_HSA-NEXT: [[VAL5:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 324; AKF_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 325; AKF_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 326; AKF_HSA-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 327; AKF_HSA-NEXT: store volatile i32 [[VAL3]], ptr addrspace(1) [[PTR]], align 4 328; AKF_HSA-NEXT: store volatile i32 [[VAL4]], ptr addrspace(1) [[PTR]], align 4 329; AKF_HSA-NEXT: store volatile i32 [[VAL5]], ptr addrspace(1) [[PTR]], align 4 330; AKF_HSA-NEXT: ret void 331; 332; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_all_workitems 333; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR9:[0-9]+]] { 334; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 335; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 336; ATTRIBUTOR_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 337; ATTRIBUTOR_HSA-NEXT: [[VAL3:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 338; ATTRIBUTOR_HSA-NEXT: [[VAL4:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 339; ATTRIBUTOR_HSA-NEXT: [[VAL5:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 340; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) [[PTR]], align 4 341; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) [[PTR]], align 4 342; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) [[PTR]], align 4 343; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL3]], ptr addrspace(1) [[PTR]], align 4 344; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL4]], ptr addrspace(1) [[PTR]], align 4 345; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL5]], ptr addrspace(1) [[PTR]], align 4 346; ATTRIBUTOR_HSA-NEXT: ret void 347; 348 %val0 = call i32 @llvm.amdgcn.workitem.id.x() 349 %val1 = call i32 @llvm.amdgcn.workitem.id.y() 350 %val2 = call i32 @llvm.amdgcn.workitem.id.z() 351 %val3 = call i32 @llvm.amdgcn.workgroup.id.x() 352 %val4 = call i32 @llvm.amdgcn.workgroup.id.y() 353 %val5 = call i32 @llvm.amdgcn.workgroup.id.z() 354 store volatile i32 %val0, ptr addrspace(1) %ptr 355 store volatile i32 %val1, ptr addrspace(1) %ptr 356 store volatile i32 %val2, ptr addrspace(1) %ptr 357 store volatile i32 %val3, ptr addrspace(1) %ptr 358 store volatile i32 %val4, ptr addrspace(1) %ptr 359 store volatile i32 %val5, ptr addrspace(1) %ptr 360 ret void 361} 362 363define amdgpu_kernel void @use_dispatch_ptr(ptr addrspace(1) %ptr) #1 { 364; AKF_HSA-LABEL: define {{[^@]+}}@use_dispatch_ptr 365; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 366; AKF_HSA-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 367; AKF_HSA-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(4) [[DISPATCH_PTR]], align 4 368; AKF_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 369; AKF_HSA-NEXT: ret void 370; 371; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_dispatch_ptr 372; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR10:[0-9]+]] { 373; ATTRIBUTOR_HSA-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 374; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(4) [[DISPATCH_PTR]], align 4 375; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 376; ATTRIBUTOR_HSA-NEXT: ret void 377; 378 %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 379 %val = load i32, ptr addrspace(4) %dispatch.ptr 380 store i32 %val, ptr addrspace(1) %ptr 381 ret void 382} 383 384define amdgpu_kernel void @use_queue_ptr(ptr addrspace(1) %ptr) #1 { 385; AKF_HSA-LABEL: define {{[^@]+}}@use_queue_ptr 386; AKF_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 387; AKF_HSA-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.queue.ptr() 388; AKF_HSA-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(4) [[DISPATCH_PTR]], align 4 389; AKF_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 390; AKF_HSA-NEXT: ret void 391; 392; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_queue_ptr 393; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR11:[0-9]+]] { 394; ATTRIBUTOR_HSA-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.queue.ptr() 395; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(4) [[DISPATCH_PTR]], align 4 396; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 397; ATTRIBUTOR_HSA-NEXT: ret void 398; 399 %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.queue.ptr() 400 %val = load i32, ptr addrspace(4) %dispatch.ptr 401 store i32 %val, ptr addrspace(1) %ptr 402 ret void 403} 404 405define amdgpu_kernel void @use_kernarg_segment_ptr(ptr addrspace(1) %ptr) #1 { 406; HSA-LABEL: define {{[^@]+}}@use_kernarg_segment_ptr 407; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 408; HSA-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() 409; HSA-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(4) [[DISPATCH_PTR]], align 4 410; HSA-NEXT: store i32 [[VAL]], ptr addrspace(1) [[PTR]], align 4 411; HSA-NEXT: ret void 412; 413 %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() 414 %val = load i32, ptr addrspace(4) %dispatch.ptr 415 store i32 %val, ptr addrspace(1) %ptr 416 ret void 417} 418 419define amdgpu_kernel void @use_group_to_flat_addrspacecast(ptr addrspace(3) %ptr) #1 { 420; AKF_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast 421; AKF_HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR1]] { 422; AKF_HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(3) [[PTR]] to ptr 423; AKF_HSA-NEXT: store volatile i32 0, ptr [[STOF]], align 4 424; AKF_HSA-NEXT: ret void 425; 426; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast 427; ATTRIBUTOR_HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR12:[0-9]+]] { 428; ATTRIBUTOR_HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(3) [[PTR]] to ptr 429; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, ptr [[STOF]], align 4 430; ATTRIBUTOR_HSA-NEXT: ret void 431; 432 %stof = addrspacecast ptr addrspace(3) %ptr to ptr 433 store volatile i32 0, ptr %stof 434 ret void 435} 436 437define amdgpu_kernel void @use_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #1 { 438; AKF_HSA-LABEL: define {{[^@]+}}@use_private_to_flat_addrspacecast 439; AKF_HSA-SAME: (ptr addrspace(5) [[PTR:%.*]]) #[[ATTR1]] { 440; AKF_HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(5) [[PTR]] to ptr 441; AKF_HSA-NEXT: store volatile i32 0, ptr [[STOF]], align 4 442; AKF_HSA-NEXT: ret void 443; 444; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_private_to_flat_addrspacecast 445; ATTRIBUTOR_HSA-SAME: (ptr addrspace(5) [[PTR:%.*]]) #[[ATTR13:[0-9]+]] { 446; ATTRIBUTOR_HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(5) [[PTR]] to ptr 447; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, ptr [[STOF]], align 4 448; ATTRIBUTOR_HSA-NEXT: ret void 449; 450 %stof = addrspacecast ptr addrspace(5) %ptr to ptr 451 store volatile i32 0, ptr %stof 452 ret void 453} 454 455define amdgpu_kernel void @use_flat_to_group_addrspacecast(ptr %ptr) #1 { 456; HSA-LABEL: define {{[^@]+}}@use_flat_to_group_addrspacecast 457; HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR1]] { 458; HSA-NEXT: [[FTOS:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(3) 459; HSA-NEXT: store volatile i32 0, ptr addrspace(3) [[FTOS]], align 4 460; HSA-NEXT: ret void 461; 462 %ftos = addrspacecast ptr %ptr to ptr addrspace(3) 463 store volatile i32 0, ptr addrspace(3) %ftos 464 ret void 465} 466 467define amdgpu_kernel void @use_flat_to_private_addrspacecast(ptr %ptr) #1 { 468; HSA-LABEL: define {{[^@]+}}@use_flat_to_private_addrspacecast 469; HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR1]] { 470; HSA-NEXT: [[FTOS:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(5) 471; HSA-NEXT: store volatile i32 0, ptr addrspace(5) [[FTOS]], align 4 472; HSA-NEXT: ret void 473; 474 %ftos = addrspacecast ptr %ptr to ptr addrspace(5) 475 store volatile i32 0, ptr addrspace(5) %ftos 476 ret void 477} 478 479; No-op addrspacecast should not use queue ptr 480define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %ptr) #1 { 481; HSA-LABEL: define {{[^@]+}}@use_global_to_flat_addrspacecast 482; HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] { 483; HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr 484; HSA-NEXT: store volatile i32 0, ptr [[STOF]], align 4 485; HSA-NEXT: ret void 486; 487 %stof = addrspacecast ptr addrspace(1) %ptr to ptr 488 store volatile i32 0, ptr %stof 489 ret void 490} 491 492define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) %ptr) #1 { 493; HSA-LABEL: define {{[^@]+}}@use_constant_to_flat_addrspacecast 494; HSA-SAME: (ptr addrspace(4) [[PTR:%.*]]) #[[ATTR1]] { 495; HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(4) [[PTR]] to ptr 496; HSA-NEXT: [[LD:%.*]] = load volatile i32, ptr [[STOF]], align 4 497; HSA-NEXT: ret void 498; 499 %stof = addrspacecast ptr addrspace(4) %ptr to ptr 500 %ld = load volatile i32, ptr %stof 501 ret void 502} 503 504define amdgpu_kernel void @use_flat_to_global_addrspacecast(ptr %ptr) #1 { 505; HSA-LABEL: define {{[^@]+}}@use_flat_to_global_addrspacecast 506; HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR1]] { 507; HSA-NEXT: [[FTOS:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(1) 508; HSA-NEXT: store volatile i32 0, ptr addrspace(1) [[FTOS]], align 4 509; HSA-NEXT: ret void 510; 511 %ftos = addrspacecast ptr %ptr to ptr addrspace(1) 512 store volatile i32 0, ptr addrspace(1) %ftos 513 ret void 514} 515 516define amdgpu_kernel void @use_flat_to_constant_addrspacecast(ptr %ptr) #1 { 517; HSA-LABEL: define {{[^@]+}}@use_flat_to_constant_addrspacecast 518; HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR1]] { 519; HSA-NEXT: [[FTOS:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(4) 520; HSA-NEXT: [[LD:%.*]] = load volatile i32, ptr addrspace(4) [[FTOS]], align 4 521; HSA-NEXT: ret void 522; 523 %ftos = addrspacecast ptr %ptr to ptr addrspace(4) 524 %ld = load volatile i32, ptr addrspace(4) %ftos 525 ret void 526} 527 528define amdgpu_kernel void @use_is_shared(ptr %ptr) #1 { 529; AKF_HSA-LABEL: define {{[^@]+}}@use_is_shared 530; AKF_HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR1]] { 531; AKF_HSA-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[PTR]]) 532; AKF_HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_SHARED]] to i32 533; AKF_HSA-NEXT: store i32 [[EXT]], ptr addrspace(1) undef, align 4 534; AKF_HSA-NEXT: ret void 535; 536; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_is_shared 537; ATTRIBUTOR_HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR12]] { 538; ATTRIBUTOR_HSA-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[PTR]]) 539; ATTRIBUTOR_HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_SHARED]] to i32 540; ATTRIBUTOR_HSA-NEXT: store i32 [[EXT]], ptr addrspace(1) undef, align 4 541; ATTRIBUTOR_HSA-NEXT: ret void 542; 543 %is.shared = call i1 @llvm.amdgcn.is.shared(ptr %ptr) 544 %ext = zext i1 %is.shared to i32 545 store i32 %ext, ptr addrspace(1) undef 546 ret void 547} 548 549define amdgpu_kernel void @use_is_private(ptr %ptr) #1 { 550; AKF_HSA-LABEL: define {{[^@]+}}@use_is_private 551; AKF_HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR1]] { 552; AKF_HSA-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[PTR]]) 553; AKF_HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_PRIVATE]] to i32 554; AKF_HSA-NEXT: store i32 [[EXT]], ptr addrspace(1) undef, align 4 555; AKF_HSA-NEXT: ret void 556; 557; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_is_private 558; ATTRIBUTOR_HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR12]] { 559; ATTRIBUTOR_HSA-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[PTR]]) 560; ATTRIBUTOR_HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_PRIVATE]] to i32 561; ATTRIBUTOR_HSA-NEXT: store i32 [[EXT]], ptr addrspace(1) undef, align 4 562; ATTRIBUTOR_HSA-NEXT: ret void 563; 564 %is.private = call i1 @llvm.amdgcn.is.private(ptr %ptr) 565 %ext = zext i1 %is.private to i32 566 store i32 %ext, ptr addrspace(1) undef 567 ret void 568} 569 570define amdgpu_kernel void @use_alloca() #1 { 571; AKF_HSA-LABEL: define {{[^@]+}}@use_alloca 572; AKF_HSA-SAME: () #[[ATTR2:[0-9]+]] { 573; AKF_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 574; AKF_HSA-NEXT: store i32 0, ptr addrspace(5) [[ALLOCA]], align 4 575; AKF_HSA-NEXT: ret void 576; 577; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_alloca 578; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] { 579; ATTRIBUTOR_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 580; ATTRIBUTOR_HSA-NEXT: store i32 0, ptr addrspace(5) [[ALLOCA]], align 4 581; ATTRIBUTOR_HSA-NEXT: ret void 582; 583 %alloca = alloca i32, addrspace(5) 584 store i32 0, ptr addrspace(5) %alloca 585 ret void 586} 587 588define amdgpu_kernel void @use_alloca_non_entry_block() #1 { 589; AKF_HSA-LABEL: define {{[^@]+}}@use_alloca_non_entry_block 590; AKF_HSA-SAME: () #[[ATTR2]] { 591; AKF_HSA-NEXT: entry: 592; AKF_HSA-NEXT: br label [[BB:%.*]] 593; AKF_HSA: bb: 594; AKF_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 595; AKF_HSA-NEXT: store i32 0, ptr addrspace(5) [[ALLOCA]], align 4 596; AKF_HSA-NEXT: ret void 597; 598; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_alloca_non_entry_block 599; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] { 600; ATTRIBUTOR_HSA-NEXT: entry: 601; ATTRIBUTOR_HSA-NEXT: br label [[BB:%.*]] 602; ATTRIBUTOR_HSA: bb: 603; ATTRIBUTOR_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 604; ATTRIBUTOR_HSA-NEXT: store i32 0, ptr addrspace(5) [[ALLOCA]], align 4 605; ATTRIBUTOR_HSA-NEXT: ret void 606; 607entry: 608 br label %bb 609 610bb: 611 %alloca = alloca i32, addrspace(5) 612 store i32 0, ptr addrspace(5) %alloca 613 ret void 614} 615 616define void @use_alloca_func() #1 { 617; AKF_HSA-LABEL: define {{[^@]+}}@use_alloca_func 618; AKF_HSA-SAME: () #[[ATTR2]] { 619; AKF_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 620; AKF_HSA-NEXT: store i32 0, ptr addrspace(5) [[ALLOCA]], align 4 621; AKF_HSA-NEXT: ret void 622; 623; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_alloca_func 624; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] { 625; ATTRIBUTOR_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 626; ATTRIBUTOR_HSA-NEXT: store i32 0, ptr addrspace(5) [[ALLOCA]], align 4 627; ATTRIBUTOR_HSA-NEXT: ret void 628; 629 %alloca = alloca i32, addrspace(5) 630 store i32 0, ptr addrspace(5) %alloca 631 ret void 632} 633 634attributes #0 = { nounwind readnone speculatable } 635attributes #1 = { nounwind } 636 637!llvm.module.flags = !{!0} 638!0 = !{i32 1, !"amdhsa_code_object_version", i32 500} 639 640;. 641; AKF_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 642; AKF_HSA: attributes #[[ATTR1]] = { nounwind } 643; AKF_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-stack-objects" } 644;. 645; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 646; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 647; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 648; ATTRIBUTOR_HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 649; ATTRIBUTOR_HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 650; ATTRIBUTOR_HSA: attributes #[[ATTR5]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 651; ATTRIBUTOR_HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" } 652; ATTRIBUTOR_HSA: attributes #[[ATTR7]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 653; ATTRIBUTOR_HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } 654; ATTRIBUTOR_HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } 655; ATTRIBUTOR_HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 656; ATTRIBUTOR_HSA: attributes #[[ATTR11]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 657; ATTRIBUTOR_HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 658; ATTRIBUTOR_HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 659;. 660; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500} 661;. 662; ATTRIBUTOR_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500} 663;. 664