xref: /llvm-project/llvm/test/CodeGen/AMDGPU/and_or.ll (revision 5cae88164e5247d01f6a814cf610fa667c9aa9a6) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
5;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
6
7; ===================================================================================
8; V_AND_OR_B32
9; ===================================================================================
10
11define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
12; VI-LABEL: and_or:
13; VI:       ; %bb.0:
14; VI-NEXT:    v_and_b32_e32 v0, v0, v1
15; VI-NEXT:    v_or_b32_e32 v0, v0, v2
16; VI-NEXT:    ; return to shader part epilog
17;
18; GFX9-LABEL: and_or:
19; GFX9:       ; %bb.0:
20; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, v2
21; GFX9-NEXT:    ; return to shader part epilog
22;
23; GFX10-LABEL: and_or:
24; GFX10:       ; %bb.0:
25; GFX10-NEXT:    v_and_or_b32 v0, v0, v1, v2
26; GFX10-NEXT:    ; return to shader part epilog
27  %x = and i32 %a, %b
28  %result = or i32 %x, %c
29  %bc = bitcast i32 %result to float
30  ret float %bc
31}
32
33; ThreeOp instruction variant not used due to Constant Bus Limitations
34define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
35; VI-LABEL: and_or_vgpr_b:
36; VI:       ; %bb.0:
37; VI-NEXT:    v_and_b32_e32 v0, s2, v0
38; VI-NEXT:    v_or_b32_e32 v0, s3, v0
39; VI-NEXT:    ; return to shader part epilog
40;
41; GFX9-LABEL: and_or_vgpr_b:
42; GFX9:       ; %bb.0:
43; GFX9-NEXT:    v_and_b32_e32 v0, s2, v0
44; GFX9-NEXT:    v_or_b32_e32 v0, s3, v0
45; GFX9-NEXT:    ; return to shader part epilog
46;
47; GFX10-LABEL: and_or_vgpr_b:
48; GFX10:       ; %bb.0:
49; GFX10-NEXT:    v_and_or_b32 v0, s2, v0, s3
50; GFX10-NEXT:    ; return to shader part epilog
51  %x = and i32 %a, %b
52  %result = or i32 %x, %c
53  %bc = bitcast i32 %result to float
54  ret float %bc
55}
56
57define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
58; VI-LABEL: and_or_vgpr_ab:
59; VI:       ; %bb.0:
60; VI-NEXT:    v_and_b32_e32 v0, v0, v1
61; VI-NEXT:    v_or_b32_e32 v0, s2, v0
62; VI-NEXT:    ; return to shader part epilog
63;
64; GFX9-LABEL: and_or_vgpr_ab:
65; GFX9:       ; %bb.0:
66; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, s2
67; GFX9-NEXT:    ; return to shader part epilog
68;
69; GFX10-LABEL: and_or_vgpr_ab:
70; GFX10:       ; %bb.0:
71; GFX10-NEXT:    v_and_or_b32 v0, v0, v1, s2
72; GFX10-NEXT:    ; return to shader part epilog
73  %x = and i32 %a, %b
74  %result = or i32 %x, %c
75  %bc = bitcast i32 %result to float
76  ret float %bc
77}
78
79define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
80; VI-LABEL: and_or_vgpr_const:
81; VI:       ; %bb.0:
82; VI-NEXT:    v_and_b32_e32 v0, 4, v0
83; VI-NEXT:    v_or_b32_e32 v0, v0, v1
84; VI-NEXT:    ; return to shader part epilog
85;
86; GFX9-LABEL: and_or_vgpr_const:
87; GFX9:       ; %bb.0:
88; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, v1
89; GFX9-NEXT:    ; return to shader part epilog
90;
91; GFX10-LABEL: and_or_vgpr_const:
92; GFX10:       ; %bb.0:
93; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, v1
94; GFX10-NEXT:    ; return to shader part epilog
95  %x = and i32 4, %a
96  %result = or i32 %x, %b
97  %bc = bitcast i32 %result to float
98  ret float %bc
99}
100
101define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
102; VI-LABEL: and_or_vgpr_const_inline_const:
103; VI:       ; %bb.0:
104; VI-NEXT:    v_and_b32_e32 v0, 20, v0
105; VI-NEXT:    v_or_b32_e32 v0, 0x808, v0
106; VI-NEXT:    ; return to shader part epilog
107;
108; GFX9-LABEL: and_or_vgpr_const_inline_const:
109; GFX9:       ; %bb.0:
110; GFX9-NEXT:    v_mov_b32_e32 v1, 0x808
111; GFX9-NEXT:    v_and_or_b32 v0, v0, 20, v1
112; GFX9-NEXT:    ; return to shader part epilog
113;
114; GFX10-LABEL: and_or_vgpr_const_inline_const:
115; GFX10:       ; %bb.0:
116; GFX10-NEXT:    v_and_or_b32 v0, v0, 20, 0x808
117; GFX10-NEXT:    ; return to shader part epilog
118  %x = and i32 20, %a
119  %result = or i32 %x, 2056
120  %bc = bitcast i32 %result to float
121  ret float %bc
122}
123
124define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
125; VI-LABEL: and_or_vgpr_inline_const_x2:
126; VI:       ; %bb.0:
127; VI-NEXT:    v_and_b32_e32 v0, 4, v0
128; VI-NEXT:    v_or_b32_e32 v0, 1, v0
129; VI-NEXT:    ; return to shader part epilog
130;
131; GFX9-LABEL: and_or_vgpr_inline_const_x2:
132; GFX9:       ; %bb.0:
133; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, 1
134; GFX9-NEXT:    ; return to shader part epilog
135;
136; GFX10-LABEL: and_or_vgpr_inline_const_x2:
137; GFX10:       ; %bb.0:
138; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, 1
139; GFX10-NEXT:    ; return to shader part epilog
140  %x = and i32 4, %a
141  %result = or i32 %x, 1
142  %bc = bitcast i32 %result to float
143  ret float %bc
144}
145