1; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tahiti | FileCheck --check-prefixes=PAL,CI --enable-var-scope %s 2; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga | FileCheck --check-prefixes=PAL,VI --enable-var-scope %s 3 4; PAL-NOT: .AMDGPU.config 5; PAL-LABEL: {{^}}simple: 6define amdgpu_kernel void @simple(ptr addrspace(1) %out) { 7entry: 8 store i32 0, ptr addrspace(1) %out 9 ret void 10} 11 12; Check code sequence for amdpal use of scratch for alloca. This is the case 13; where the high half of the address comes from s_getpc. 14 15; PAL-LABEL: {{^}}scratch: 16; PAL: s_getpc_b64 s[[[GITPTR:[0-9]+]]: 17; PAL: s_mov_b32 s[[GITPTR]], s0 18; PAL: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]: 19; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]: 20 21define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, ptr addrspace(5) %out) { 22entry: 23 %v = alloca [2 x i32], addrspace(5) 24 store <2 x i32> %in, ptr addrspace(5) %v 25 %e = getelementptr [2 x i32], ptr addrspace(5) %v, i32 0, i32 %idx 26 %x = load i32, ptr addrspace(5) %e 27 store i32 %x, ptr addrspace(5) %out 28 ret void 29} 30 31; Check code sequence for amdpal use of scratch for alloca. This is the case 32; where the amdgpu-git-ptr-high function attribute gives the high half of the 33; address to use. 34; Looks like you can't do arithmetic on a filecheck variable, so we can't test 35; that the s_movk_i32 is into a reg that is one more than the following 36; s_mov_b32. 37 38; PAL-LABEL: {{^}}scratch2: 39; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234 40; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0 41; PAL: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]: 42; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]: 43 44define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, ptr addrspace(5) %out) #0 { 45entry: 46 %v = alloca [2 x i32], addrspace(5) 47 store <2 x i32> %in, ptr addrspace(5) %v 48 %e = getelementptr [2 x i32], ptr addrspace(5) %v, i32 0, i32 %idx 49 %x = load i32, ptr addrspace(5) %e 50 store i32 %x, ptr addrspace(5) %out 51 ret void 52} 53 54; Check code sequence for amdpal use of scratch for alloca in a compute shader. 55; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset 56; 0 in a graphics shader. 57; Prior to GCN3 s_load_dword offsets are dwords, so the offset will be 0x4. 58 59; PAL-LABEL: {{^}}scratch2_cs: 60; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234 61; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0 62; CI: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:{{[0-9]+\]}}, 0x4 63; VI: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:{{[0-9]+\]}}, 0x10 64; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]: 65 66define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 { 67entry: 68 %v = alloca [3 x i32], addrspace(5) 69 %v1 = getelementptr [3 x i32], ptr addrspace(5) %v, i32 0, i32 1 70 store i32 %extra, ptr addrspace(5) %v 71 store <2 x i32> %in, ptr addrspace(5) %v1 72 %e = getelementptr [2 x i32], ptr addrspace(5) %v1, i32 0, i32 %idx 73 %x = load i32, ptr addrspace(5) %e 74 %xf = bitcast i32 %x to float 75 call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %xf, ptr addrspace(8) undef, i32 0, i32 0, i32 0) 76 ret void 77} 78 79attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" } 80 81declare void @llvm.amdgcn.raw.ptr.buffer.store.f32(float, ptr addrspace(8), i32, i32, i32 immarg) 82 83 84; PAL: .amdgpu_pal_metadata 85; PAL-NEXT: --- 86; PAL-NEXT: amdpal.pipelines: 87; PAL-NEXT: - .hardware_stages: 88; PAL-NEXT: .cs: 89; PAL-NEXT: .entry_point_symbol: scratch2_cs 90; PAL-NEXT: .scratch_memory_size: 0x10 91; PAL-NEXT: .sgpr_count: 0x 92; PAL-NEXT: .vgpr_count: 0x 93