1; RUN: llc < %s -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc < %s -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE %s 3; RUN: llc < %s -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC 4; RUN: llc < %s -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA %s 5; RUN: llc < %s -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s 6; RUN: llc < %s -show-mc-encoding -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE-VECT -check-prefix=SI -check-prefix=FUNC %s 7; RUN: llc < %s -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s 8 9; RUN: opt < %s -S -mtriple=amdgcn-unknown-amdhsa -data-layout=A5 -mcpu=kaveri -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector | FileCheck -enable-var-scope -check-prefix=HSAOPT -check-prefix=OPT %s 10; RUN: opt < %s -S -mtriple=amdgcn-unknown-unknown -data-layout=A5 -mcpu=kaveri -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector | FileCheck -enable-var-scope -check-prefix=NOHSAOPT -check-prefix=OPT %s 11 12; RUN: llc < %s -mtriple=r600 -mcpu=cypress -disable-promote-alloca-to-vector | FileCheck %s -check-prefix=R600 -check-prefix=FUNC 13; RUN: llc < %s -mtriple=r600 -mcpu=cypress | FileCheck %s -check-prefix=R600-VECT -check-prefix=FUNC 14 15; HSAOPT: @mova_same_clause.stack = internal unnamed_addr addrspace(3) global [256 x [5 x i32]] poison, align 4 16; HSAOPT: @high_alignment.stack = internal unnamed_addr addrspace(3) global [256 x [8 x i32]] poison, align 16 17 18 19; FUNC-LABEL: {{^}}mova_same_clause: 20; OPT-LABEL: @mova_same_clause( 21 22; R600: LDS_WRITE 23; R600: LDS_WRITE 24; R600: LDS_READ 25; R600: LDS_READ 26 27; HSA-PROMOTE: .amdhsa_group_segment_fixed_size 5120 28 29; HSA-PROMOTE: s_load_dwordx2 s[{{[0-9:]+}}], s[4:5], 0x1 30 31; SI-PROMOTE: ds_write_b32 32; SI-PROMOTE: ds_write_b32 33; SI-PROMOTE: ds_read_b32 34; SI-PROMOTE: ds_read_b32 35 36; FIXME: Creating the emergency stack slots causes us to over-estimate scratch 37; by 4 bytes. 38; HSA-ALLOCA: .amdhsa_private_segment_fixed_size 24 39 40; HSA-ALLOCA: s_add_i32 s12, s12, s17 41; HSA-ALLOCA-DAG: s_mov_b32 flat_scratch_lo, s13 42; HSA-ALLOCA-DAG: s_lshr_b32 flat_scratch_hi, s12, 8 43 44; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; encoding: [0x00,0x10,0x70,0xe0 45; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; encoding: [0x00,0x10,0x70,0xe0 46 47 48; HSAOPT: [[DISPATCH_PTR:%[0-9]+]] = call noalias nonnull dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 49; HSAOPT: [[GEP0:%[0-9]+]] = getelementptr inbounds i32, ptr addrspace(4) [[DISPATCH_PTR]], i64 1 50; HSAOPT: [[LDXY:%[0-9]+]] = load i32, ptr addrspace(4) [[GEP0]], align 4, !invariant.load !1 51; HSAOPT: [[GEP1:%[0-9]+]] = getelementptr inbounds i32, ptr addrspace(4) [[DISPATCH_PTR]], i64 2 52; HSAOPT: [[LDZU:%[0-9]+]] = load i32, ptr addrspace(4) [[GEP1]], align 4, !range !2, !invariant.load !1 53; HSAOPT: [[EXTRACTY:%[0-9]+]] = lshr i32 [[LDXY]], 16 54 55; HSAOPT: [[WORKITEM_ID_X:%[0-9]+]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.x() 56; HSAOPT: [[WORKITEM_ID_Y:%[0-9]+]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.y() 57; HSAOPT: [[WORKITEM_ID_Z:%[0-9]+]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.z() 58 59; HSAOPT: [[Y_SIZE_X_Z_SIZE:%[0-9]+]] = mul nuw nsw i32 [[EXTRACTY]], [[LDZU]] 60; HSAOPT: [[YZ_X_XID:%[0-9]+]] = mul i32 [[Y_SIZE_X_Z_SIZE]], [[WORKITEM_ID_X]] 61; HSAOPT: [[Y_X_Z_SIZE:%[0-9]+]] = mul nuw nsw i32 [[WORKITEM_ID_Y]], [[LDZU]] 62; HSAOPT: [[ADD_YZ_X_X_YZ_SIZE:%[0-9]+]] = add i32 [[YZ_X_XID]], [[Y_X_Z_SIZE]] 63; HSAOPT: [[ADD_ZID:%[0-9]+]] = add i32 [[ADD_YZ_X_X_YZ_SIZE]], [[WORKITEM_ID_Z]] 64 65; HSAOPT: [[LOCAL_GEP:%[0-9]+]] = getelementptr inbounds [256 x [5 x i32]], ptr addrspace(3) @mova_same_clause.stack, i32 0, i32 [[ADD_ZID]] 66; HSAOPT: %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(3) [[LOCAL_GEP]], i32 0, i32 {{%[0-9]+}} 67; HSAOPT: %arrayidx3 = getelementptr inbounds [5 x i32], ptr addrspace(3) [[LOCAL_GEP]], i32 0, i32 {{%[0-9]+}} 68; HSAOPT: %arrayidx12 = getelementptr inbounds [5 x i32], ptr addrspace(3) [[LOCAL_GEP]], i32 0, i32 1 69 70 71; NOHSAOPT: call range(i32 0, 257) i32 @llvm.r600.read.local.size.y() 72; NOHSAOPT: call range(i32 0, 257) i32 @llvm.r600.read.local.size.z() 73; NOHSAOPT: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.x() 74; NOHSAOPT: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.y() 75; NOHSAOPT: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.z() 76define amdgpu_kernel void @mova_same_clause(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #0 { 77entry: 78 %stack = alloca [5 x i32], align 4, addrspace(5) 79 %0 = load i32, ptr addrspace(1) %in, align 4 80 %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %0 81 store i32 4, ptr addrspace(5) %arrayidx1, align 4 82 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %in, i32 1 83 %1 = load i32, ptr addrspace(1) %arrayidx2, align 4 84 %arrayidx3 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %1 85 store i32 5, ptr addrspace(5) %arrayidx3, align 4 86 %2 = load i32, ptr addrspace(5) %stack, align 4 87 store i32 %2, ptr addrspace(1) %out, align 4 88 %arrayidx12 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 1 89 %3 = load i32, ptr addrspace(5) %arrayidx12 90 %arrayidx13 = getelementptr inbounds i32, ptr addrspace(1) %out, i32 1 91 store i32 %3, ptr addrspace(1) %arrayidx13 92 ret void 93} 94 95; OPT-LABEL: @high_alignment( 96; OPT: getelementptr inbounds [256 x [8 x i32]], ptr addrspace(3) @high_alignment.stack, i32 0, i32 %{{[0-9]+}} 97define amdgpu_kernel void @high_alignment(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #0 { 98entry: 99 %stack = alloca [8 x i32], align 16, addrspace(5) 100 %0 = load i32, ptr addrspace(1) %in, align 4 101 %arrayidx1 = getelementptr inbounds [8 x i32], ptr addrspace(5) %stack, i32 0, i32 %0 102 store i32 4, ptr addrspace(5) %arrayidx1, align 4 103 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %in, i32 1 104 %1 = load i32, ptr addrspace(1) %arrayidx2, align 4 105 %arrayidx3 = getelementptr inbounds [8 x i32], ptr addrspace(5) %stack, i32 0, i32 %1 106 store i32 5, ptr addrspace(5) %arrayidx3, align 4 107 %2 = load i32, ptr addrspace(5) %stack, align 4 108 store i32 %2, ptr addrspace(1) %out, align 4 109 %arrayidx12 = getelementptr inbounds [8 x i32], ptr addrspace(5) %stack, i32 0, i32 1 110 %3 = load i32, ptr addrspace(5) %arrayidx12 111 %arrayidx13 = getelementptr inbounds i32, ptr addrspace(1) %out, i32 1 112 store i32 %3, ptr addrspace(1) %arrayidx13 113 ret void 114} 115 116; FUNC-LABEL: {{^}}no_replace_inbounds_gep: 117; OPT-LABEL: @no_replace_inbounds_gep( 118; OPT: alloca [5 x i32] 119 120; SI-NOT: ds_write 121define amdgpu_kernel void @no_replace_inbounds_gep(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #0 { 122entry: 123 %stack = alloca [5 x i32], align 4, addrspace(5) 124 %0 = load i32, ptr addrspace(1) %in, align 4 125 %arrayidx1 = getelementptr [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %0 126 store i32 4, ptr addrspace(5) %arrayidx1, align 4 127 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %in, i32 1 128 %1 = load i32, ptr addrspace(1) %arrayidx2, align 4 129 %arrayidx3 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %1 130 store i32 5, ptr addrspace(5) %arrayidx3, align 4 131 %2 = load i32, ptr addrspace(5) %stack, align 4 132 store i32 %2, ptr addrspace(1) %out, align 4 133 %arrayidx12 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 1 134 %3 = load i32, ptr addrspace(5) %arrayidx12 135 %arrayidx13 = getelementptr inbounds i32, ptr addrspace(1) %out, i32 1 136 store i32 %3, ptr addrspace(1) %arrayidx13 137 ret void 138} 139 140; This test checks that the stack offset is calculated correctly for structs. 141; All register loads/stores should be optimized away, so there shouldn't be 142; any MOVA instructions. 143; 144; XXX: This generated code has unnecessary MOVs, we should be able to optimize 145; this. 146 147; FUNC-LABEL: {{^}}multiple_structs: 148; OPT-LABEL: @multiple_structs( 149 150; R600-NOT: MOVA_INT 151; SI-NOT: v_movrel 152; SI-NOT: v_movrel 153%struct.point = type { i32, i32 } 154 155define amdgpu_kernel void @multiple_structs(ptr addrspace(1) %out) #0 { 156entry: 157 %a = alloca %struct.point, addrspace(5) 158 %b = alloca %struct.point, addrspace(5) 159 %a.y.ptr = getelementptr %struct.point, ptr addrspace(5) %a, i32 0, i32 1 160 %b.y.ptr = getelementptr %struct.point, ptr addrspace(5) %b, i32 0, i32 1 161 store i32 0, ptr addrspace(5) %a 162 store i32 1, ptr addrspace(5) %a.y.ptr 163 store i32 2, ptr addrspace(5) %b 164 store i32 3, ptr addrspace(5) %b.y.ptr 165 %a.indirect = load i32, ptr addrspace(5) %a 166 %b.indirect = load i32, ptr addrspace(5) %b 167 %0 = add i32 %a.indirect, %b.indirect 168 store i32 %0, ptr addrspace(1) %out 169 ret void 170} 171 172; Test direct access of a private array inside a loop. The private array 173; loads and stores should be lowered to copies, so there shouldn't be any 174; MOVA instructions. 175 176; FUNC-LABEL: {{^}}direct_loop: 177; R600-NOT: MOVA_INT 178; SI-NOT: v_movrel 179 180define amdgpu_kernel void @direct_loop(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { 181entry: 182 %prv_array_const = alloca [2 x i32], addrspace(5) 183 %prv_array = alloca [2 x i32], addrspace(5) 184 %a = load i32, ptr addrspace(1) %in 185 %b_src_ptr = getelementptr inbounds i32, ptr addrspace(1) %in, i32 1 186 %b = load i32, ptr addrspace(1) %b_src_ptr 187 store i32 %a, ptr addrspace(5) %prv_array_const 188 %b_dst_ptr = getelementptr inbounds [2 x i32], ptr addrspace(5) %prv_array_const, i32 0, i32 1 189 store i32 %b, ptr addrspace(5) %b_dst_ptr 190 br label %for.body 191 192for.body: 193 %inc = phi i32 [0, %entry], [%count, %for.body] 194 %x = load i32, ptr addrspace(5) %prv_array_const 195 %y = load i32, ptr addrspace(5) %prv_array 196 %xy = add i32 %x, %y 197 store i32 %xy, ptr addrspace(5) %prv_array 198 %count = add i32 %inc, 1 199 %done = icmp eq i32 %count, 4095 200 br i1 %done, label %for.end, label %for.body 201 202for.end: 203 %value = load i32, ptr addrspace(5) %prv_array 204 store i32 %value, ptr addrspace(1) %out 205 ret void 206} 207 208; FUNC-LABEL: {{^}}short_array: 209 210; R600-VECT: MOVA_INT 211 212; SI-ALLOCA-DAG: buffer_store_short v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:2 ; encoding: [0x02,0x00,0x68,0xe0 213; SI-ALLOCA-DAG: buffer_store_short v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; encoding: [0x00,0x00,0x68,0xe0 214; Loaded value is 0 or 1, so sext will become zext, so we get buffer_load_ushort instead of buffer_load_sshort. 215; SI-ALLOCA: buffer_load_sshort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 216 217; SI-PROMOTE-VECT: s_load_dword [[IDX:s[0-9]+]] 218; SI-PROMOTE-VECT: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 4 219; SI-PROMOTE-VECT: s_lshr_b32 [[SREG:s[0-9]+]], 0x10000, [[SCALED_IDX]] 220; SI-PROMOTE-VECT: s_and_b32 s{{[0-9]+}}, [[SREG]], 1 221define amdgpu_kernel void @short_array(ptr addrspace(1) %out, i32 %index) #0 { 222entry: 223 %0 = alloca [2 x i16], addrspace(5) 224 %1 = getelementptr inbounds [2 x i16], ptr addrspace(5) %0, i32 0, i32 1 225 store i16 0, ptr addrspace(5) %0 226 store i16 1, ptr addrspace(5) %1 227 %2 = getelementptr inbounds [2 x i16], ptr addrspace(5) %0, i32 0, i32 %index 228 %3 = load i16, ptr addrspace(5) %2 229 %4 = sext i16 %3 to i32 230 store i32 %4, ptr addrspace(1) %out 231 ret void 232} 233 234; FUNC-LABEL: {{^}}char_array: 235 236; R600-VECT: MOVA_INT 237 238; SI-PROMOTE-VECT-DAG: s_lshl_b32 239; SI-PROMOTE-VECT-DAG: s_lshr_b32 240 241; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; encoding: [0x00,0x00,0x60,0xe0 242; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:1 ; encoding: [0x01,0x00,0x60,0xe0 243define amdgpu_kernel void @char_array(ptr addrspace(1) %out, i32 %index) #0 { 244entry: 245 %0 = alloca [2 x i8], addrspace(5) 246 %1 = getelementptr inbounds [2 x i8], ptr addrspace(5) %0, i32 0, i32 1 247 store i8 0, ptr addrspace(5) %0 248 store i8 1, ptr addrspace(5) %1 249 %2 = getelementptr inbounds [2 x i8], ptr addrspace(5) %0, i32 0, i32 %index 250 %3 = load i8, ptr addrspace(5) %2 251 %4 = sext i8 %3 to i32 252 store i32 %4, ptr addrspace(1) %out 253 ret void 254} 255 256; Test that two stack objects are not stored in the same register 257; The second stack object should be in T3.X 258; FUNC-LABEL: {{^}}no_overlap: 259; 260; A total of 5 bytes should be allocated and used. 261; SI: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; 262define amdgpu_kernel void @no_overlap(ptr addrspace(1) %out, i32 %in) #0 { 263entry: 264 %0 = alloca [3 x i8], align 1, addrspace(5) 265 %1 = alloca [2 x i8], align 1, addrspace(5) 266 %2 = getelementptr [3 x i8], ptr addrspace(5) %0, i32 0, i32 1 267 %3 = getelementptr [3 x i8], ptr addrspace(5) %0, i32 0, i32 2 268 %4 = getelementptr [2 x i8], ptr addrspace(5) %1, i32 0, i32 1 269 store i8 0, ptr addrspace(5) %0 270 store i8 1, ptr addrspace(5) %2 271 store i8 2, ptr addrspace(5) %3 272 store i8 1, ptr addrspace(5) %1 273 store i8 0, ptr addrspace(5) %4 274 %5 = getelementptr [3 x i8], ptr addrspace(5) %0, i32 0, i32 %in 275 %6 = getelementptr [2 x i8], ptr addrspace(5) %1, i32 0, i32 %in 276 %7 = load i8, ptr addrspace(5) %5 277 %8 = load i8, ptr addrspace(5) %6 278 %9 = add i8 %7, %8 279 %10 = sext i8 %9 to i32 280 store i32 %10, ptr addrspace(1) %out 281 ret void 282} 283 284define amdgpu_kernel void @char_array_array(ptr addrspace(1) %out, i32 %index) #0 { 285entry: 286 %alloca = alloca [2 x [2 x i8]], addrspace(5) 287 %gep1 = getelementptr [2 x [2 x i8]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1 288 store i8 0, ptr addrspace(5) %alloca 289 store i8 1, ptr addrspace(5) %gep1 290 %gep2 = getelementptr [2 x [2 x i8]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 %index 291 %load = load i8, ptr addrspace(5) %gep2 292 %sext = sext i8 %load to i32 293 store i32 %sext, ptr addrspace(1) %out 294 ret void 295} 296 297define amdgpu_kernel void @i32_array_array(ptr addrspace(1) %out, i32 %index) #0 { 298entry: 299 %alloca = alloca [2 x [2 x i32]], addrspace(5) 300 %gep1 = getelementptr [2 x [2 x i32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1 301 store i32 0, ptr addrspace(5) %alloca 302 store i32 1, ptr addrspace(5) %gep1 303 %gep2 = getelementptr [2 x [2 x i32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 %index 304 %load = load i32, ptr addrspace(5) %gep2 305 store i32 %load, ptr addrspace(1) %out 306 ret void 307} 308 309define amdgpu_kernel void @i64_array_array(ptr addrspace(1) %out, i32 %index) #0 { 310entry: 311 %alloca = alloca [2 x [2 x i64]], addrspace(5) 312 %gep1 = getelementptr [2 x [2 x i64]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1 313 store i64 0, ptr addrspace(5) %alloca 314 store i64 1, ptr addrspace(5) %gep1 315 %gep2 = getelementptr [2 x [2 x i64]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 %index 316 %load = load i64, ptr addrspace(5) %gep2 317 store i64 %load, ptr addrspace(1) %out 318 ret void 319} 320 321%struct.pair32 = type { i32, i32 } 322 323define amdgpu_kernel void @struct_array_array(ptr addrspace(1) %out, i32 %index) #0 { 324entry: 325 %alloca = alloca [2 x [2 x %struct.pair32]], addrspace(5) 326 %gep0 = getelementptr [2 x [2 x %struct.pair32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 0, i32 1 327 %gep1 = getelementptr [2 x [2 x %struct.pair32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1, i32 1 328 store i32 0, ptr addrspace(5) %gep0 329 store i32 1, ptr addrspace(5) %gep1 330 %gep2 = getelementptr [2 x [2 x %struct.pair32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 %index, i32 0 331 %load = load i32, ptr addrspace(5) %gep2 332 store i32 %load, ptr addrspace(1) %out 333 ret void 334} 335 336define amdgpu_kernel void @struct_pair32_array(ptr addrspace(1) %out, i32 %index) #0 { 337entry: 338 %alloca = alloca [2 x %struct.pair32], addrspace(5) 339 %gep0 = getelementptr [2 x %struct.pair32], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1 340 %gep1 = getelementptr [2 x %struct.pair32], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0 341 store i32 0, ptr addrspace(5) %gep0 342 store i32 1, ptr addrspace(5) %gep1 343 %gep2 = getelementptr [2 x %struct.pair32], ptr addrspace(5) %alloca, i32 0, i32 %index, i32 0 344 %load = load i32, ptr addrspace(5) %gep2 345 store i32 %load, ptr addrspace(1) %out 346 ret void 347} 348 349define amdgpu_kernel void @select_private(ptr addrspace(1) %out, i32 %in) nounwind { 350entry: 351 %tmp = alloca [2 x i32], addrspace(5) 352 %tmp2 = getelementptr [2 x i32], ptr addrspace(5) %tmp, i32 0, i32 1 353 store i32 0, ptr addrspace(5) %tmp 354 store i32 1, ptr addrspace(5) %tmp2 355 %cmp = icmp eq i32 %in, 0 356 %sel = select i1 %cmp, ptr addrspace(5) %tmp, ptr addrspace(5) %tmp2 357 %load = load i32, ptr addrspace(5) %sel 358 store i32 %load, ptr addrspace(1) %out 359 ret void 360} 361 362; AMDGPUPromoteAlloca does not know how to handle ptrtoint. When it 363; finds one, it should stop trying to promote. 364 365; FUNC-LABEL: ptrtoint: 366; SI-NOT: ds_write 367; SI: s_add_i32 [[S_ADD_OFFSET:s[0-9]+]], s{{[0-9]+}}, 5 368; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen 369; SI: v_mov_b32_e32 [[V_ADD_OFFSET:v[0-9]+]], [[S_ADD_OFFSET]] 370; SI: buffer_load_dword v{{[0-9]+}}, [[V_ADD_OFFSET:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offen ; 371define amdgpu_kernel void @ptrtoint(ptr addrspace(1) %out, i32 %a, i32 %b) #0 { 372 %alloca = alloca [16 x i32], addrspace(5) 373 %tmp0 = getelementptr [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %a 374 store i32 5, ptr addrspace(5) %tmp0 375 %tmp1 = ptrtoint ptr addrspace(5) %alloca to i32 376 %tmp2 = add i32 %tmp1, 5 377 %tmp3 = inttoptr i32 %tmp2 to ptr addrspace(5) 378 %tmp4 = getelementptr i32, ptr addrspace(5) %tmp3, i32 %b 379 %tmp5 = load i32, ptr addrspace(5) %tmp4 380 store i32 %tmp5, ptr addrspace(1) %out 381 ret void 382} 383 384; OPT-LABEL: @pointer_typed_alloca( 385; OPT: getelementptr inbounds [256 x ptr addrspace(1)], ptr addrspace(3) @pointer_typed_alloca.A.addr, i32 0, i32 %{{[0-9]+}} 386; OPT: load ptr addrspace(1), ptr addrspace(3) %{{[0-9]+}}, align 4 387define amdgpu_kernel void @pointer_typed_alloca(ptr addrspace(1) %A) #1 { 388entry: 389 %A.addr = alloca ptr addrspace(1), align 4, addrspace(5) 390 store ptr addrspace(1) %A, ptr addrspace(5) %A.addr, align 4 391 %ld0 = load ptr addrspace(1), ptr addrspace(5) %A.addr, align 4 392 store i32 1, ptr addrspace(1) %ld0, align 4 393 %ld1 = load ptr addrspace(1), ptr addrspace(5) %A.addr, align 4 394 %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %ld1, i32 1 395 store i32 2, ptr addrspace(1) %arrayidx1, align 4 396 %ld2 = load ptr addrspace(1), ptr addrspace(5) %A.addr, align 4 397 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %ld2, i32 2 398 store i32 3, ptr addrspace(1) %arrayidx2, align 4 399 ret void 400} 401 402; FUNC-LABEL: v16i32_stack: 403 404; R600: MOVA_INT 405; R600: MOVA_INT 406; R600: MOVA_INT 407; R600: MOVA_INT 408; R600: MOVA_INT 409; R600: MOVA_INT 410; R600: MOVA_INT 411; R600: MOVA_INT 412; R600: MOVA_INT 413; R600: MOVA_INT 414; R600: MOVA_INT 415; R600: MOVA_INT 416; R600: MOVA_INT 417; R600: MOVA_INT 418; R600: MOVA_INT 419; R600: MOVA_INT 420 421; SI: buffer_load_dword 422; SI: buffer_load_dword 423; SI: buffer_load_dword 424; SI: buffer_load_dword 425; SI: buffer_load_dword 426; SI: buffer_load_dword 427; SI: buffer_load_dword 428; SI: buffer_load_dword 429; SI: buffer_load_dword 430; SI: buffer_load_dword 431; SI: buffer_load_dword 432; SI: buffer_load_dword 433; SI: buffer_load_dword 434; SI: buffer_load_dword 435; SI: buffer_load_dword 436; SI: buffer_load_dword 437 438define amdgpu_kernel void @v16i32_stack(ptr addrspace(1) %out, i32 %a) { 439 %alloca = alloca [2 x <16 x i32>], addrspace(5) 440 %tmp0 = getelementptr [2 x <16 x i32>], ptr addrspace(5) %alloca, i32 0, i32 %a 441 %tmp5 = load <16 x i32>, ptr addrspace(5) %tmp0 442 store <16 x i32> %tmp5, ptr addrspace(1) %out 443 ret void 444} 445 446; FUNC-LABEL: v16float_stack: 447 448; R600: MOVA_INT 449; R600: MOVA_INT 450; R600: MOVA_INT 451; R600: MOVA_INT 452; R600: MOVA_INT 453; R600: MOVA_INT 454; R600: MOVA_INT 455; R600: MOVA_INT 456; R600: MOVA_INT 457; R600: MOVA_INT 458; R600: MOVA_INT 459; R600: MOVA_INT 460; R600: MOVA_INT 461; R600: MOVA_INT 462; R600: MOVA_INT 463; R600: MOVA_INT 464 465; SI: buffer_load_dword 466; SI: buffer_load_dword 467; SI: buffer_load_dword 468; SI: buffer_load_dword 469; SI: buffer_load_dword 470; SI: buffer_load_dword 471; SI: buffer_load_dword 472; SI: buffer_load_dword 473; SI: buffer_load_dword 474; SI: buffer_load_dword 475; SI: buffer_load_dword 476; SI: buffer_load_dword 477; SI: buffer_load_dword 478; SI: buffer_load_dword 479; SI: buffer_load_dword 480; SI: buffer_load_dword 481 482define amdgpu_kernel void @v16float_stack(ptr addrspace(1) %out, i32 %a) { 483 %alloca = alloca [2 x <16 x float>], addrspace(5) 484 %tmp0 = getelementptr [2 x <16 x float>], ptr addrspace(5) %alloca, i32 0, i32 %a 485 %tmp5 = load <16 x float>, ptr addrspace(5) %tmp0 486 store <16 x float> %tmp5, ptr addrspace(1) %out 487 ret void 488} 489 490; FUNC-LABEL: v2float_stack: 491 492; R600: MOVA_INT 493; R600: MOVA_INT 494 495; SI: buffer_load_dword 496; SI: buffer_load_dword 497 498define amdgpu_kernel void @v2float_stack(ptr addrspace(1) %out, i32 %a) { 499 %alloca = alloca [16 x <2 x float>], addrspace(5) 500 %tmp0 = getelementptr [16 x <2 x float>], ptr addrspace(5) %alloca, i32 0, i32 %a 501 %tmp5 = load <2 x float>, ptr addrspace(5) %tmp0 502 store <2 x float> %tmp5, ptr addrspace(1) %out 503 ret void 504} 505 506; OPT-LABEL: @direct_alloca_read_0xi32( 507; OPT: store [0 x i32] poison, ptr addrspace(3) 508; OPT: load [0 x i32], ptr addrspace(3) 509define amdgpu_kernel void @direct_alloca_read_0xi32(ptr addrspace(1) %out, i32 %index) { 510entry: 511 %tmp = alloca [0 x i32], addrspace(5) 512 store [0 x i32] [], ptr addrspace(5) %tmp 513 %load = load [0 x i32], ptr addrspace(5) %tmp 514 store [0 x i32] %load, ptr addrspace(1) %out 515 ret void 516} 517 518; OPT-LABEL: @direct_alloca_read_1xi32( 519; OPT: store [1 x i32] zeroinitializer, ptr addrspace(3) 520; OPT: load [1 x i32], ptr addrspace(3) 521define amdgpu_kernel void @direct_alloca_read_1xi32(ptr addrspace(1) %out, i32 %index) { 522entry: 523 %tmp = alloca [1 x i32], addrspace(5) 524 store [1 x i32] [i32 0], ptr addrspace(5) %tmp 525 %load = load [1 x i32], ptr addrspace(5) %tmp 526 store [1 x i32] %load, ptr addrspace(1) %out 527 ret void 528} 529 530attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,2" "amdgpu-flat-work-group-size"="1,256" } 531attributes #1 = { nounwind "amdgpu-flat-work-group-size"="1,256" } 532 533!llvm.module.flags = !{!99} 534!99 = !{i32 1, !"amdhsa_code_object_version", i32 400} 535 536; HSAOPT: !1 = !{} 537