1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 4 2; RUN: opt < %s -passes=amdgpu-sw-lower-lds -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s 3 4; Test to check if LDS accesses are lowered correctly when LDS is passed as function 5; argument to non-kernel. 6 7@lds_var = internal addrspace(3) global [1024 x i32] poison, align 4 8 9;. 10; CHECK: @llvm.amdgcn.sw.lds.my_kernel = internal addrspace(3) global ptr poison, no_sanitize_address, align 4, !absolute_symbol [[META0:![0-9]+]] 11; CHECK: @llvm.amdgcn.sw.lds.my_kernel.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.my_kernel.md.type { %llvm.amdgcn.sw.lds.my_kernel.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.my_kernel.md.item { i32 32, i32 4096, i32 5120 } }, no_sanitize_address 12; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.my_kernel], no_sanitize_address 13;. 14define void @my_function(ptr addrspace(3) %lds_arg) sanitize_address { 15; CHECK-LABEL: define void @my_function( 16; CHECK-SAME: ptr addrspace(3) [[LDS_ARG:%.*]]) #[[ATTR0:[0-9]+]] { 17; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() 18; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr addrspace(3)], ptr addrspace(1) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 [[TMP1]] 19; CHECK-NEXT: [[TMP3:%.*]] = load ptr addrspace(3), ptr addrspace(1) [[TMP2]], align 4 20; CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(1), ptr addrspace(3) [[TMP3]], align 8 21; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr addrspace(3) [[LDS_ARG]] to i32 22; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP4]], i32 [[TMP5]] 23; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr addrspace(1) [[TMP6]] to i64 24; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP7]], 3 25; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 2147450880 26; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr 27; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1 28; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i8 [[TMP11]], 0 29; CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP7]], 7 30; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP13]], 3 31; CHECK-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i8 32; CHECK-NEXT: [[TMP16:%.*]] = icmp sge i8 [[TMP15]], [[TMP11]] 33; CHECK-NEXT: [[TMP17:%.*]] = and i1 [[TMP12]], [[TMP16]] 34; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP17]]) 35; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i64 [[TMP18]], 0 36; CHECK-NEXT: br i1 [[TMP19]], label [[ASAN_REPORT:%.*]], label [[TMP22:%.*]], !prof [[PROF1:![0-9]+]] 37; CHECK: asan.report: 38; CHECK-NEXT: br i1 [[TMP17]], label [[TMP20:%.*]], label [[TMP21:%.*]] 39; CHECK: 20: 40; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP7]]) #[[ATTR7:[0-9]+]] 41; CHECK-NEXT: call void @llvm.amdgcn.unreachable() 42; CHECK-NEXT: br label [[TMP21]] 43; CHECK: 21: 44; CHECK-NEXT: br label [[TMP22]] 45; CHECK: 22: 46; CHECK-NEXT: [[LDS_VAL:%.*]] = load i32, ptr addrspace(1) [[TMP6]], align 4 47; CHECK-NEXT: [[NEW_LDS_VAL:%.*]] = add i32 [[LDS_VAL]], 1 48; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr addrspace(3) [[LDS_ARG]] to i32 49; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP4]], i32 [[TMP24]] 50; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr addrspace(1) [[TMP25]] to i64 51; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP26]], 3 52; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], 2147450880 53; CHECK-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to ptr 54; CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[TMP29]], align 1 55; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i8 [[TMP30]], 0 56; CHECK-NEXT: [[TMP32:%.*]] = and i64 [[TMP26]], 7 57; CHECK-NEXT: [[TMP33:%.*]] = add i64 [[TMP32]], 3 58; CHECK-NEXT: [[TMP34:%.*]] = trunc i64 [[TMP33]] to i8 59; CHECK-NEXT: [[TMP35:%.*]] = icmp sge i8 [[TMP34]], [[TMP30]] 60; CHECK-NEXT: [[TMP36:%.*]] = and i1 [[TMP31]], [[TMP35]] 61; CHECK-NEXT: [[TMP37:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP36]]) 62; CHECK-NEXT: [[TMP38:%.*]] = icmp ne i64 [[TMP37]], 0 63; CHECK-NEXT: br i1 [[TMP38]], label [[ASAN_REPORT1:%.*]], label [[TMP41:%.*]], !prof [[PROF1]] 64; CHECK: asan.report1: 65; CHECK-NEXT: br i1 [[TMP36]], label [[TMP39:%.*]], label [[TMP40:%.*]] 66; CHECK: 39: 67; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP26]]) #[[ATTR7]] 68; CHECK-NEXT: call void @llvm.amdgcn.unreachable() 69; CHECK-NEXT: br label [[TMP40]] 70; CHECK: 40: 71; CHECK-NEXT: br label [[TMP41]] 72; CHECK: 41: 73; CHECK-NEXT: store i32 [[NEW_LDS_VAL]], ptr addrspace(1) [[TMP25]], align 4 74; CHECK-NEXT: ret void 75; 76 %lds_val = load i32, ptr addrspace(3) %lds_arg, align 4 77 %new_lds_val = add i32 %lds_val, 1 78 store i32 %new_lds_val, ptr addrspace(3) %lds_arg, align 4 79 ret void 80} 81 82define amdgpu_kernel void @my_kernel() sanitize_address { 83; CHECK-LABEL: define amdgpu_kernel void @my_kernel( 84; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META2:![0-9]+]] { 85; CHECK-NEXT: WId: 86; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 87; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 88; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 89; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]] 90; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]] 91; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 92; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]] 93; CHECK: Malloc: 94; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MY_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i32 0, i32 1, i32 0), align 4 95; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MY_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i32 0, i32 1, i32 2), align 4 96; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP11]], [[TMP12]] 97; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP14]] to i64 98; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress(i32 0) 99; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP10]] to i64 100; CHECK-NEXT: [[TMP16:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP13]], i64 [[TMP15]]) 101; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP16]] to ptr addrspace(1) 102; CHECK-NEXT: store ptr addrspace(1) [[TMP6]], ptr addrspace(3) @llvm.amdgcn.sw.lds.my_kernel, align 8 103; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP6]], i64 8 104; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr addrspace(1) [[TMP21]] to i64 105; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP22]], i64 24) 106; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP6]], i64 4128 107; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr addrspace(1) [[TMP23]] to i64 108; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP24]], i64 1024) 109; CHECK-NEXT: br label [[TMP7]] 110; CHECK: 18: 111; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ] 112; CHECK-NEXT: call void @llvm.amdgcn.s.barrier() 113; CHECK-NEXT: [[TMP17:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.my_kernel, align 8 114; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MY_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i32 0, i32 1, i32 0), align 4 115; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.my_kernel, i32 [[TMP8]] 116; CHECK-NEXT: [[LDS_PTR:%.*]] = getelementptr [1024 x i32], ptr addrspace(3) [[TMP9]], i32 0, i32 0 117; CHECK-NEXT: call void @my_function(ptr addrspace(3) [[LDS_PTR]]) 118; CHECK-NEXT: br label [[CONDFREE:%.*]] 119; CHECK: CondFree: 120; CHECK-NEXT: call void @llvm.amdgcn.s.barrier() 121; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]] 122; CHECK: Free: 123; CHECK-NEXT: [[TMP18:%.*]] = call ptr @llvm.returnaddress(i32 0) 124; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[TMP18]] to i64 125; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr addrspace(1) [[TMP17]] to i64 126; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP20]], i64 [[TMP19]]) 127; CHECK-NEXT: br label [[END]] 128; CHECK: End: 129; CHECK-NEXT: ret void 130; 131 %lds_ptr = getelementptr [1024 x i32], ptr addrspace(3) @lds_var, i32 0, i32 0 132 call void @my_function(ptr addrspace(3) %lds_ptr) 133 ret void 134} 135 136!llvm.module.flags = !{!0} 137!0 = !{i32 4, !"nosanitize_address", i32 1} 138 139;. 140; CHECK: attributes #[[ATTR0]] = { sanitize_address } 141; CHECK: attributes #[[ATTR1]] = { sanitize_address "amdgpu-lds-size"="8" } 142; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 143; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) } 144; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nounwind willreturn } 145; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nofree nounwind willreturn memory(none) } 146; CHECK: attributes #[[ATTR6:[0-9]+]] = { convergent nocallback nofree nounwind } 147; CHECK: attributes #[[ATTR7]] = { nomerge } 148;. 149; CHECK: [[META0]] = !{i32 0, i32 1} 150; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575} 151; CHECK: [[META2]] = !{i32 0} 152;. 153