1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -passes=amdgpu-codegenprepare %s | FileCheck -check-prefix=SI %s 3; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -amdgpu-codegenprepare %s | FileCheck -check-prefix=VI %s 4; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -amdgpu-codegenprepare-mul24=0 -amdgpu-codegenprepare %s | FileCheck -check-prefix=DISABLED %s 5 6define i16 @mul_i16(i16 %lhs, i16 %rhs) { 7; SI-LABEL: @mul_i16( 8; SI-NEXT: [[TMP1:%.*]] = zext i16 [[LHS:%.*]] to i32 9; SI-NEXT: [[TMP2:%.*]] = zext i16 [[RHS:%.*]] to i32 10; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP1]], i32 [[TMP2]]) 11; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i16 12; SI-NEXT: ret i16 [[MUL]] 13; 14; VI-LABEL: @mul_i16( 15; VI-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]] 16; VI-NEXT: ret i16 [[MUL]] 17; 18; DISABLED-LABEL: @mul_i16( 19; DISABLED-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]] 20; DISABLED-NEXT: ret i16 [[MUL]] 21; 22 %mul = mul i16 %lhs, %rhs 23 ret i16 %mul 24} 25 26define i32 @smul24_i32(i32 %lhs, i32 %rhs) { 27; SI-LABEL: @smul24_i32( 28; SI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8 29; SI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8 30; SI-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 8 31; SI-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 8 32; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[LHS24]], i32 [[RHS24]]) 33; SI-NEXT: ret i32 [[MUL]] 34; 35; VI-LABEL: @smul24_i32( 36; VI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8 37; VI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8 38; VI-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 8 39; VI-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 8 40; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[LHS24]], i32 [[RHS24]]) 41; VI-NEXT: ret i32 [[MUL]] 42; 43; DISABLED-LABEL: @smul24_i32( 44; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8 45; DISABLED-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8 46; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 8 47; DISABLED-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 8 48; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 49; DISABLED-NEXT: ret i32 [[MUL]] 50; 51 %shl.lhs = shl i32 %lhs, 8 52 %lhs24 = ashr i32 %shl.lhs, 8 53 %shl.rhs = shl i32 %rhs, 8 54 %rhs24 = ashr i32 %shl.rhs, 8 55 %mul = mul i32 %lhs24, %rhs24 56 ret i32 %mul 57} 58 59define <2 x i8> @mul_v1i16(<1 x i16> %arg) { 60; SI-LABEL: @mul_v1i16( 61; SI-NEXT: BB: 62; SI-NEXT: [[TMP0:%.*]] = extractelement <1 x i16> [[ARG:%.*]], i64 0 63; SI-NEXT: [[TMP1:%.*]] = zext i16 [[TMP0]] to i32 64; SI-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP1]], i32 42) 65; SI-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16 66; SI-NEXT: [[MUL:%.*]] = insertelement <1 x i16> poison, i16 [[TMP3]], i64 0 67; SI-NEXT: [[CAST:%.*]] = bitcast <1 x i16> [[MUL]] to <2 x i8> 68; SI-NEXT: ret <2 x i8> [[CAST]] 69; 70; VI-LABEL: @mul_v1i16( 71; VI-NEXT: BB: 72; VI-NEXT: [[MUL:%.*]] = mul <1 x i16> [[ARG:%.*]], splat (i16 42) 73; VI-NEXT: [[CAST:%.*]] = bitcast <1 x i16> [[MUL]] to <2 x i8> 74; VI-NEXT: ret <2 x i8> [[CAST]] 75; 76; DISABLED-LABEL: @mul_v1i16( 77; DISABLED-NEXT: BB: 78; DISABLED-NEXT: [[MUL:%.*]] = mul <1 x i16> [[ARG:%.*]], splat (i16 42) 79; DISABLED-NEXT: [[CAST:%.*]] = bitcast <1 x i16> [[MUL]] to <2 x i8> 80; DISABLED-NEXT: ret <2 x i8> [[CAST]] 81; 82BB: 83 %mul = mul <1 x i16> %arg, <i16 42> 84 %cast = bitcast <1 x i16> %mul to <2 x i8> 85 ret <2 x i8> %cast 86} 87 88define <1 x i8> @mul_v1i8(<1 x i8> %arg) { 89; SI-LABEL: @mul_v1i8( 90; SI-NEXT: BB: 91; SI-NEXT: [[TMP0:%.*]] = extractelement <1 x i8> [[ARG:%.*]], i64 0 92; SI-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32 93; SI-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP1]], i32 42) 94; SI-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8 95; SI-NEXT: [[MUL:%.*]] = insertelement <1 x i8> poison, i8 [[TMP3]], i64 0 96; SI-NEXT: ret <1 x i8> [[MUL]] 97; 98; VI-LABEL: @mul_v1i8( 99; VI-NEXT: BB: 100; VI-NEXT: [[MUL:%.*]] = mul <1 x i8> [[ARG:%.*]], splat (i8 42) 101; VI-NEXT: ret <1 x i8> [[MUL]] 102; 103; DISABLED-LABEL: @mul_v1i8( 104; DISABLED-NEXT: BB: 105; DISABLED-NEXT: [[MUL:%.*]] = mul <1 x i8> [[ARG:%.*]], splat (i8 42) 106; DISABLED-NEXT: ret <1 x i8> [[MUL]] 107; 108BB: 109 %mul = mul <1 x i8> %arg, <i8 42> 110 ret <1 x i8> %mul 111} 112 113define <2 x i32> @smul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 114; SI-LABEL: @smul24_v2i32( 115; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], splat (i32 8) 116; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], splat (i32 8) 117; SI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], splat (i32 8) 118; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[SHL_RHS]], splat (i32 8) 119; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 120; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 121; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 122; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 123; SI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[TMP1]], i32 [[TMP3]]) 124; SI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[TMP2]], i32 [[TMP4]]) 125; SI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> poison, i32 [[TMP5]], i64 0 126; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 127; SI-NEXT: ret <2 x i32> [[MUL]] 128; 129; VI-LABEL: @smul24_v2i32( 130; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], splat (i32 8) 131; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], splat (i32 8) 132; VI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], splat (i32 8) 133; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[SHL_RHS]], splat (i32 8) 134; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 135; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 136; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 137; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 138; VI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[TMP1]], i32 [[TMP3]]) 139; VI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[TMP2]], i32 [[TMP4]]) 140; VI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> poison, i32 [[TMP5]], i64 0 141; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 142; VI-NEXT: ret <2 x i32> [[MUL]] 143; 144; DISABLED-LABEL: @smul24_v2i32( 145; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], splat (i32 8) 146; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], splat (i32 8) 147; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], splat (i32 8) 148; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[SHL_RHS]], splat (i32 8) 149; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]] 150; DISABLED-NEXT: ret <2 x i32> [[MUL]] 151; 152 %shl.lhs = shl <2 x i32> %lhs, <i32 8, i32 8> 153 %lhs24 = ashr <2 x i32> %shl.lhs, <i32 8, i32 8> 154 %shl.rhs = shl <2 x i32> %rhs, <i32 8, i32 8> 155 %rhs24 = ashr <2 x i32> %shl.rhs, <i32 8, i32 8> 156 %mul = mul <2 x i32> %lhs24, %rhs24 157 ret <2 x i32> %mul 158} 159 160define i32 @umul24_i32(i32 %lhs, i32 %rhs) { 161; SI-LABEL: @umul24_i32( 162; SI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215 163; SI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215 164; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[LHS24]], i32 [[RHS24]]) 165; SI-NEXT: ret i32 [[MUL]] 166; 167; VI-LABEL: @umul24_i32( 168; VI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215 169; VI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215 170; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[LHS24]], i32 [[RHS24]]) 171; VI-NEXT: ret i32 [[MUL]] 172; 173; DISABLED-LABEL: @umul24_i32( 174; DISABLED-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215 175; DISABLED-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215 176; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 177; DISABLED-NEXT: ret i32 [[MUL]] 178; 179 %lhs24 = and i32 %lhs, 16777215 180 %rhs24 = and i32 %rhs, 16777215 181 %mul = mul i32 %lhs24, %rhs24 182 ret i32 %mul 183} 184 185define <2 x i32> @umul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 186; SI-LABEL: @umul24_v2i32( 187; SI-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], splat (i32 16777215) 188; SI-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], splat (i32 16777215) 189; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 190; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 191; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 192; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 193; SI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP1]], i32 [[TMP3]]) 194; SI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP2]], i32 [[TMP4]]) 195; SI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> poison, i32 [[TMP5]], i64 0 196; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 197; SI-NEXT: ret <2 x i32> [[MUL]] 198; 199; VI-LABEL: @umul24_v2i32( 200; VI-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], splat (i32 16777215) 201; VI-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], splat (i32 16777215) 202; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 203; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 204; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 205; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 206; VI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP1]], i32 [[TMP3]]) 207; VI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP2]], i32 [[TMP4]]) 208; VI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> poison, i32 [[TMP5]], i64 0 209; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 210; VI-NEXT: ret <2 x i32> [[MUL]] 211; 212; DISABLED-LABEL: @umul24_v2i32( 213; DISABLED-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], splat (i32 16777215) 214; DISABLED-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], splat (i32 16777215) 215; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]] 216; DISABLED-NEXT: ret <2 x i32> [[MUL]] 217; 218 %lhs24 = and <2 x i32> %lhs, <i32 16777215, i32 16777215> 219 %rhs24 = and <2 x i32> %rhs, <i32 16777215, i32 16777215> 220 %mul = mul <2 x i32> %lhs24, %rhs24 221 ret <2 x i32> %mul 222} 223 224define i64 @smul24_i64(i64 %lhs, i64 %rhs) { 225; SI-LABEL: @smul24_i64( 226; SI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40 227; SI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40 228; SI-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 40 229; SI-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 40 230; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 231; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 232; SI-NEXT: [[MUL:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP1]], i32 [[TMP2]]) 233; SI-NEXT: ret i64 [[MUL]] 234; 235; VI-LABEL: @smul24_i64( 236; VI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40 237; VI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40 238; VI-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 40 239; VI-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 40 240; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 241; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 242; VI-NEXT: [[MUL:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP1]], i32 [[TMP2]]) 243; VI-NEXT: ret i64 [[MUL]] 244; 245; DISABLED-LABEL: @smul24_i64( 246; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40 247; DISABLED-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40 248; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 40 249; DISABLED-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 40 250; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 251; DISABLED-NEXT: ret i64 [[MUL]] 252; 253 %shl.lhs = shl i64 %lhs, 40 254 %lhs24 = ashr i64 %shl.lhs, 40 255 %shl.rhs = shl i64 %rhs, 40 256 %rhs24 = ashr i64 %shl.rhs, 40 257 %mul = mul i64 %lhs24, %rhs24 258 ret i64 %mul 259} 260 261define i64 @smul24_i64_2(i64 %lhs, i64 %rhs) { 262; SI-LABEL: @smul24_i64_2( 263; SI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 49 264; SI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 49 265; SI-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 49 266; SI-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 49 267; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 268; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 269; SI-NEXT: [[MUL:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP1]], i32 [[TMP2]]) 270; SI-NEXT: ret i64 [[MUL]] 271; 272; VI-LABEL: @smul24_i64_2( 273; VI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 49 274; VI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 49 275; VI-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 49 276; VI-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 49 277; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 278; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 279; VI-NEXT: [[MUL:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP1]], i32 [[TMP2]]) 280; VI-NEXT: ret i64 [[MUL]] 281; 282; DISABLED-LABEL: @smul24_i64_2( 283; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 49 284; DISABLED-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 49 285; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 49 286; DISABLED-NEXT: [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 49 287; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 288; DISABLED-NEXT: ret i64 [[MUL]] 289; 290 %shl.lhs = shl i64 %lhs, 49 291 %lhs24 = ashr i64 %shl.lhs, 49 292 %shl.rhs = shl i64 %rhs, 49 293 %rhs24 = ashr i64 %shl.rhs, 49 294 %mul = mul i64 %lhs24, %rhs24 295 ret i64 %mul 296} 297 298define i64 @smul24_i64_3(i64 %lhs, i64 %rhs) { 299; SI-LABEL: @smul24_i64_3( 300; SI-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i16 301; SI-NEXT: [[LHS24:%.*]] = sext i16 [[LHS_TRUNC]] to i64 302; SI-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i17 303; SI-NEXT: [[RHS24:%.*]] = sext i17 [[RHS_TRUNC]] to i64 304; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 305; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 306; SI-NEXT: [[MUL:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP1]], i32 [[TMP2]]) 307; SI-NEXT: ret i64 [[MUL]] 308; 309; VI-LABEL: @smul24_i64_3( 310; VI-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i16 311; VI-NEXT: [[LHS24:%.*]] = sext i16 [[LHS_TRUNC]] to i64 312; VI-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i17 313; VI-NEXT: [[RHS24:%.*]] = sext i17 [[RHS_TRUNC]] to i64 314; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 315; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 316; VI-NEXT: [[MUL:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP1]], i32 [[TMP2]]) 317; VI-NEXT: ret i64 [[MUL]] 318; 319; DISABLED-LABEL: @smul24_i64_3( 320; DISABLED-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i16 321; DISABLED-NEXT: [[LHS24:%.*]] = sext i16 [[LHS_TRUNC]] to i64 322; DISABLED-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i17 323; DISABLED-NEXT: [[RHS24:%.*]] = sext i17 [[RHS_TRUNC]] to i64 324; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 325; DISABLED-NEXT: ret i64 [[MUL]] 326; 327 %lhs.trunc = trunc i64 %lhs to i16 328 %lhs24 = sext i16 %lhs.trunc to i64 329 %rhs.trunc = trunc i64 %rhs to i17 330 %rhs24 = sext i17 %rhs.trunc to i64 331 %mul = mul i64 %lhs24, %rhs24 332 ret i64 %mul 333} 334 335define i64 @smul24_i64_4(i64 %lhs, i64 %rhs) { 336; SI-LABEL: @smul24_i64_4( 337; SI-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i24 338; SI-NEXT: [[LHS24:%.*]] = sext i24 [[LHS_TRUNC]] to i64 339; SI-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i25 340; SI-NEXT: [[RHS24:%.*]] = sext i25 [[RHS_TRUNC]] to i64 341; SI-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 342; SI-NEXT: ret i64 [[MUL]] 343; 344; VI-LABEL: @smul24_i64_4( 345; VI-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i24 346; VI-NEXT: [[LHS24:%.*]] = sext i24 [[LHS_TRUNC]] to i64 347; VI-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i25 348; VI-NEXT: [[RHS24:%.*]] = sext i25 [[RHS_TRUNC]] to i64 349; VI-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 350; VI-NEXT: ret i64 [[MUL]] 351; 352; DISABLED-LABEL: @smul24_i64_4( 353; DISABLED-NEXT: [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i24 354; DISABLED-NEXT: [[LHS24:%.*]] = sext i24 [[LHS_TRUNC]] to i64 355; DISABLED-NEXT: [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i25 356; DISABLED-NEXT: [[RHS24:%.*]] = sext i25 [[RHS_TRUNC]] to i64 357; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 358; DISABLED-NEXT: ret i64 [[MUL]] 359; 360 %lhs.trunc = trunc i64 %lhs to i24 361 %lhs24 = sext i24 %lhs.trunc to i64 362 %rhs.trunc = trunc i64 %rhs to i25 363 %rhs24 = sext i25 %rhs.trunc to i64 364 %mul = mul i64 %lhs24, %rhs24 365 ret i64 %mul 366} 367 368define i64 @umul24_i64(i64 %lhs, i64 %rhs) { 369; SI-LABEL: @umul24_i64( 370; SI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215 371; SI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215 372; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 373; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 374; SI-NEXT: [[MUL:%.*]] = call i64 @llvm.amdgcn.mul.u24.i64(i32 [[TMP1]], i32 [[TMP2]]) 375; SI-NEXT: ret i64 [[MUL]] 376; 377; VI-LABEL: @umul24_i64( 378; VI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215 379; VI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215 380; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 381; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 382; VI-NEXT: [[MUL:%.*]] = call i64 @llvm.amdgcn.mul.u24.i64(i32 [[TMP1]], i32 [[TMP2]]) 383; VI-NEXT: ret i64 [[MUL]] 384; 385; DISABLED-LABEL: @umul24_i64( 386; DISABLED-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215 387; DISABLED-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215 388; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 389; DISABLED-NEXT: ret i64 [[MUL]] 390; 391 %lhs24 = and i64 %lhs, 16777215 392 %rhs24 = and i64 %rhs, 16777215 393 %mul = mul i64 %lhs24, %rhs24 394 ret i64 %mul 395} 396 397define i64 @umul24_i64_2(i64 %lhs, i64 %rhs) { 398; SI-LABEL: @umul24_i64_2( 399; SI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 65535 400; SI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 65535 401; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 402; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 403; SI-NEXT: [[MUL:%.*]] = call i64 @llvm.amdgcn.mul.u24.i64(i32 [[TMP1]], i32 [[TMP2]]) 404; SI-NEXT: ret i64 [[MUL]] 405; 406; VI-LABEL: @umul24_i64_2( 407; VI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 65535 408; VI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 65535 409; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 410; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 411; VI-NEXT: [[MUL:%.*]] = call i64 @llvm.amdgcn.mul.u24.i64(i32 [[TMP1]], i32 [[TMP2]]) 412; VI-NEXT: ret i64 [[MUL]] 413; 414; DISABLED-LABEL: @umul24_i64_2( 415; DISABLED-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 65535 416; DISABLED-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 65535 417; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 418; DISABLED-NEXT: ret i64 [[MUL]] 419; 420 %lhs24 = and i64 %lhs, 65535 421 %rhs24 = and i64 %rhs, 65535 422 %mul = mul i64 %lhs24, %rhs24 423 ret i64 %mul 424} 425 426define i31 @smul24_i31(i31 %lhs, i31 %rhs) { 427; SI-LABEL: @smul24_i31( 428; SI-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7 429; SI-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7 430; SI-NEXT: [[SHL_RHS:%.*]] = shl i31 [[RHS:%.*]], 7 431; SI-NEXT: [[RHS24:%.*]] = ashr i31 [[SHL_RHS]], 7 432; SI-NEXT: [[TMP1:%.*]] = sext i31 [[LHS24]] to i32 433; SI-NEXT: [[TMP2:%.*]] = sext i31 [[RHS24]] to i32 434; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[TMP1]], i32 [[TMP2]]) 435; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 436; SI-NEXT: ret i31 [[MUL]] 437; 438; VI-LABEL: @smul24_i31( 439; VI-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7 440; VI-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7 441; VI-NEXT: [[SHL_RHS:%.*]] = shl i31 [[RHS:%.*]], 7 442; VI-NEXT: [[RHS24:%.*]] = ashr i31 [[SHL_RHS]], 7 443; VI-NEXT: [[TMP1:%.*]] = sext i31 [[LHS24]] to i32 444; VI-NEXT: [[TMP2:%.*]] = sext i31 [[RHS24]] to i32 445; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[TMP1]], i32 [[TMP2]]) 446; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 447; VI-NEXT: ret i31 [[MUL]] 448; 449; DISABLED-LABEL: @smul24_i31( 450; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7 451; DISABLED-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7 452; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i31 [[RHS:%.*]], 7 453; DISABLED-NEXT: [[RHS24:%.*]] = ashr i31 [[SHL_RHS]], 7 454; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]] 455; DISABLED-NEXT: ret i31 [[MUL]] 456; 457 %shl.lhs = shl i31 %lhs, 7 458 %lhs24 = ashr i31 %shl.lhs, 7 459 %shl.rhs = shl i31 %rhs, 7 460 %rhs24 = ashr i31 %shl.rhs, 7 461 %mul = mul i31 %lhs24, %rhs24 462 ret i31 %mul 463} 464 465define i31 @umul24_i31(i31 %lhs, i31 %rhs) { 466; SI-LABEL: @umul24_i31( 467; SI-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215 468; SI-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215 469; SI-NEXT: [[TMP1:%.*]] = zext i31 [[LHS24]] to i32 470; SI-NEXT: [[TMP2:%.*]] = zext i31 [[RHS24]] to i32 471; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP1]], i32 [[TMP2]]) 472; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 473; SI-NEXT: ret i31 [[MUL]] 474; 475; VI-LABEL: @umul24_i31( 476; VI-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215 477; VI-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215 478; VI-NEXT: [[TMP1:%.*]] = zext i31 [[LHS24]] to i32 479; VI-NEXT: [[TMP2:%.*]] = zext i31 [[RHS24]] to i32 480; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP1]], i32 [[TMP2]]) 481; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 482; VI-NEXT: ret i31 [[MUL]] 483; 484; DISABLED-LABEL: @umul24_i31( 485; DISABLED-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215 486; DISABLED-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215 487; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]] 488; DISABLED-NEXT: ret i31 [[MUL]] 489; 490 %lhs24 = and i31 %lhs, 16777215 491 %rhs24 = and i31 %rhs, 16777215 492 %mul = mul i31 %lhs24, %rhs24 493 ret i31 %mul 494} 495 496define <2 x i31> @umul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) { 497; SI-LABEL: @umul24_v2i31( 498; SI-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], splat (i31 16777215) 499; SI-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], splat (i31 16777215) 500; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 501; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 502; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 503; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 504; SI-NEXT: [[TMP5:%.*]] = zext i31 [[TMP1]] to i32 505; SI-NEXT: [[TMP6:%.*]] = zext i31 [[TMP3]] to i32 506; SI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP5]], i32 [[TMP6]]) 507; SI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 508; SI-NEXT: [[TMP9:%.*]] = zext i31 [[TMP2]] to i32 509; SI-NEXT: [[TMP10:%.*]] = zext i31 [[TMP4]] to i32 510; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP9]], i32 [[TMP10]]) 511; SI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 512; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> poison, i31 [[TMP8]], i64 0 513; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 514; SI-NEXT: ret <2 x i31> [[MUL]] 515; 516; VI-LABEL: @umul24_v2i31( 517; VI-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], splat (i31 16777215) 518; VI-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], splat (i31 16777215) 519; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 520; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 521; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 522; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 523; VI-NEXT: [[TMP5:%.*]] = zext i31 [[TMP1]] to i32 524; VI-NEXT: [[TMP6:%.*]] = zext i31 [[TMP3]] to i32 525; VI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP5]], i32 [[TMP6]]) 526; VI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 527; VI-NEXT: [[TMP9:%.*]] = zext i31 [[TMP2]] to i32 528; VI-NEXT: [[TMP10:%.*]] = zext i31 [[TMP4]] to i32 529; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.u24.i32(i32 [[TMP9]], i32 [[TMP10]]) 530; VI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 531; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> poison, i31 [[TMP8]], i64 0 532; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 533; VI-NEXT: ret <2 x i31> [[MUL]] 534; 535; DISABLED-LABEL: @umul24_v2i31( 536; DISABLED-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], splat (i31 16777215) 537; DISABLED-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], splat (i31 16777215) 538; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]] 539; DISABLED-NEXT: ret <2 x i31> [[MUL]] 540; 541 %lhs24 = and <2 x i31> %lhs, <i31 16777215, i31 16777215> 542 %rhs24 = and <2 x i31> %rhs, <i31 16777215, i31 16777215> 543 %mul = mul <2 x i31> %lhs24, %rhs24 544 ret <2 x i31> %mul 545} 546 547define <2 x i31> @smul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) { 548; SI-LABEL: @smul24_v2i31( 549; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], splat (i31 8) 550; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], splat (i31 8) 551; SI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], splat (i31 8) 552; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[SHL_RHS]], splat (i31 8) 553; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 554; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 555; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 556; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 557; SI-NEXT: [[TMP5:%.*]] = sext i31 [[TMP1]] to i32 558; SI-NEXT: [[TMP6:%.*]] = sext i31 [[TMP3]] to i32 559; SI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[TMP5]], i32 [[TMP6]]) 560; SI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 561; SI-NEXT: [[TMP9:%.*]] = sext i31 [[TMP2]] to i32 562; SI-NEXT: [[TMP10:%.*]] = sext i31 [[TMP4]] to i32 563; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[TMP9]], i32 [[TMP10]]) 564; SI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 565; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> poison, i31 [[TMP8]], i64 0 566; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 567; SI-NEXT: ret <2 x i31> [[MUL]] 568; 569; VI-LABEL: @smul24_v2i31( 570; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], splat (i31 8) 571; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], splat (i31 8) 572; VI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], splat (i31 8) 573; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[SHL_RHS]], splat (i31 8) 574; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 575; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 576; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 577; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 578; VI-NEXT: [[TMP5:%.*]] = sext i31 [[TMP1]] to i32 579; VI-NEXT: [[TMP6:%.*]] = sext i31 [[TMP3]] to i32 580; VI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[TMP5]], i32 [[TMP6]]) 581; VI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 582; VI-NEXT: [[TMP9:%.*]] = sext i31 [[TMP2]] to i32 583; VI-NEXT: [[TMP10:%.*]] = sext i31 [[TMP4]] to i32 584; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24.i32(i32 [[TMP9]], i32 [[TMP10]]) 585; VI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 586; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> poison, i31 [[TMP8]], i64 0 587; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 588; VI-NEXT: ret <2 x i31> [[MUL]] 589; 590; DISABLED-LABEL: @smul24_v2i31( 591; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], splat (i31 8) 592; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], splat (i31 8) 593; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], splat (i31 8) 594; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[SHL_RHS]], splat (i31 8) 595; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]] 596; DISABLED-NEXT: ret <2 x i31> [[MUL]] 597; 598 %shl.lhs = shl <2 x i31> %lhs, <i31 8, i31 8> 599 %lhs24 = ashr <2 x i31> %shl.lhs, <i31 8, i31 8> 600 %shl.rhs = shl <2 x i31> %rhs, <i31 8, i31 8> 601 %rhs24 = ashr <2 x i31> %shl.rhs, <i31 8, i31 8> 602 %mul = mul <2 x i31> %lhs24, %rhs24 603 ret <2 x i31> %mul 604} 605 606define i33 @smul24_i33(i33 %lhs, i33 %rhs) { 607; SI-LABEL: @smul24_i33( 608; SI-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9 609; SI-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9 610; SI-NEXT: [[SHL_RHS:%.*]] = shl i33 [[RHS:%.*]], 9 611; SI-NEXT: [[RHS24:%.*]] = ashr i33 [[SHL_RHS]], 9 612; SI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32 613; SI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32 614; SI-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP1]], i32 [[TMP2]]) 615; SI-NEXT: [[MUL:%.*]] = trunc i64 [[TMP3]] to i33 616; SI-NEXT: ret i33 [[MUL]] 617; 618; VI-LABEL: @smul24_i33( 619; VI-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9 620; VI-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9 621; VI-NEXT: [[SHL_RHS:%.*]] = shl i33 [[RHS:%.*]], 9 622; VI-NEXT: [[RHS24:%.*]] = ashr i33 [[SHL_RHS]], 9 623; VI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32 624; VI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32 625; VI-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP1]], i32 [[TMP2]]) 626; VI-NEXT: [[MUL:%.*]] = trunc i64 [[TMP3]] to i33 627; VI-NEXT: ret i33 [[MUL]] 628; 629; DISABLED-LABEL: @smul24_i33( 630; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9 631; DISABLED-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9 632; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i33 [[RHS:%.*]], 9 633; DISABLED-NEXT: [[RHS24:%.*]] = ashr i33 [[SHL_RHS]], 9 634; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]] 635; DISABLED-NEXT: ret i33 [[MUL]] 636; 637 %shl.lhs = shl i33 %lhs, 9 638 %lhs24 = ashr i33 %shl.lhs, 9 639 %shl.rhs = shl i33 %rhs, 9 640 %rhs24 = ashr i33 %shl.rhs, 9 641 %mul = mul i33 %lhs24, %rhs24 642 ret i33 %mul 643} 644 645define i33 @umul24_i33(i33 %lhs, i33 %rhs) { 646; SI-LABEL: @umul24_i33( 647; SI-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215 648; SI-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215 649; SI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32 650; SI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32 651; SI-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.mul.u24.i64(i32 [[TMP1]], i32 [[TMP2]]) 652; SI-NEXT: [[MUL:%.*]] = trunc i64 [[TMP3]] to i33 653; SI-NEXT: ret i33 [[MUL]] 654; 655; VI-LABEL: @umul24_i33( 656; VI-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215 657; VI-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215 658; VI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32 659; VI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32 660; VI-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.mul.u24.i64(i32 [[TMP1]], i32 [[TMP2]]) 661; VI-NEXT: [[MUL:%.*]] = trunc i64 [[TMP3]] to i33 662; VI-NEXT: ret i33 [[MUL]] 663; 664; DISABLED-LABEL: @umul24_i33( 665; DISABLED-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215 666; DISABLED-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215 667; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]] 668; DISABLED-NEXT: ret i33 [[MUL]] 669; 670 %lhs24 = and i33 %lhs, 16777215 671 %rhs24 = and i33 %rhs, 16777215 672 %mul = mul i33 %lhs24, %rhs24 673 ret i33 %mul 674} 675 676define i32 @smul25_i32(i32 %lhs, i32 %rhs) { 677; SI-LABEL: @smul25_i32( 678; SI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7 679; SI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7 680; SI-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 7 681; SI-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 7 682; SI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 683; SI-NEXT: ret i32 [[MUL]] 684; 685; VI-LABEL: @smul25_i32( 686; VI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7 687; VI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7 688; VI-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 7 689; VI-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 7 690; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 691; VI-NEXT: ret i32 [[MUL]] 692; 693; DISABLED-LABEL: @smul25_i32( 694; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7 695; DISABLED-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7 696; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 7 697; DISABLED-NEXT: [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 7 698; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 699; DISABLED-NEXT: ret i32 [[MUL]] 700; 701 %shl.lhs = shl i32 %lhs, 7 702 %lhs24 = ashr i32 %shl.lhs, 7 703 %shl.rhs = shl i32 %rhs, 7 704 %rhs24 = ashr i32 %shl.rhs, 7 705 %mul = mul i32 %lhs24, %rhs24 706 ret i32 %mul 707} 708 709define i32 @umul25_i32(i32 %lhs, i32 %rhs) { 710; SI-LABEL: @umul25_i32( 711; SI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431 712; SI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431 713; SI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 714; SI-NEXT: ret i32 [[MUL]] 715; 716; VI-LABEL: @umul25_i32( 717; VI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431 718; VI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431 719; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 720; VI-NEXT: ret i32 [[MUL]] 721; 722; DISABLED-LABEL: @umul25_i32( 723; DISABLED-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431 724; DISABLED-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431 725; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 726; DISABLED-NEXT: ret i32 [[MUL]] 727; 728 %lhs24 = and i32 %lhs, 33554431 729 %rhs24 = and i32 %rhs, 33554431 730 %mul = mul i32 %lhs24, %rhs24 731 ret i32 %mul 732} 733 734define <2 x i33> @smul24_v2i33(<2 x i33> %lhs, <2 x i33> %rhs) { 735; SI-LABEL: @smul24_v2i33( 736; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], splat (i33 9) 737; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], splat (i33 9) 738; SI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], splat (i33 9) 739; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[SHL_RHS]], splat (i33 9) 740; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i33> [[LHS24]], i64 0 741; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i33> [[LHS24]], i64 1 742; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i33> [[RHS24]], i64 0 743; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i33> [[RHS24]], i64 1 744; SI-NEXT: [[TMP5:%.*]] = trunc i33 [[TMP1]] to i32 745; SI-NEXT: [[TMP6:%.*]] = trunc i33 [[TMP3]] to i32 746; SI-NEXT: [[TMP7:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP5]], i32 [[TMP6]]) 747; SI-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i33 748; SI-NEXT: [[TMP9:%.*]] = trunc i33 [[TMP2]] to i32 749; SI-NEXT: [[TMP10:%.*]] = trunc i33 [[TMP4]] to i32 750; SI-NEXT: [[TMP11:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP9]], i32 [[TMP10]]) 751; SI-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i33 752; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i33> poison, i33 [[TMP8]], i64 0 753; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i33> [[TMP13]], i33 [[TMP12]], i64 1 754; SI-NEXT: ret <2 x i33> [[MUL]] 755; 756; VI-LABEL: @smul24_v2i33( 757; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], splat (i33 9) 758; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], splat (i33 9) 759; VI-NEXT: [[SHL_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], splat (i33 9) 760; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[SHL_RHS]], splat (i33 9) 761; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i33> [[LHS24]], i64 0 762; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i33> [[LHS24]], i64 1 763; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i33> [[RHS24]], i64 0 764; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i33> [[RHS24]], i64 1 765; VI-NEXT: [[TMP5:%.*]] = trunc i33 [[TMP1]] to i32 766; VI-NEXT: [[TMP6:%.*]] = trunc i33 [[TMP3]] to i32 767; VI-NEXT: [[TMP7:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP5]], i32 [[TMP6]]) 768; VI-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i33 769; VI-NEXT: [[TMP9:%.*]] = trunc i33 [[TMP2]] to i32 770; VI-NEXT: [[TMP10:%.*]] = trunc i33 [[TMP4]] to i32 771; VI-NEXT: [[TMP11:%.*]] = call i64 @llvm.amdgcn.mul.i24.i64(i32 [[TMP9]], i32 [[TMP10]]) 772; VI-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i33 773; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i33> poison, i33 [[TMP8]], i64 0 774; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i33> [[TMP13]], i33 [[TMP12]], i64 1 775; VI-NEXT: ret <2 x i33> [[MUL]] 776; 777; DISABLED-LABEL: @smul24_v2i33( 778; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], splat (i33 9) 779; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], splat (i33 9) 780; DISABLED-NEXT: [[SHL_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], splat (i33 9) 781; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[SHL_RHS]], splat (i33 9) 782; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i33> [[LHS24]], [[RHS24]] 783; DISABLED-NEXT: ret <2 x i33> [[MUL]] 784; 785 %shl.lhs = shl <2 x i33> %lhs, <i33 9, i33 9> 786 %lhs24 = ashr <2 x i33> %shl.lhs, <i33 9, i33 9> 787 %shl.rhs = shl <2 x i33> %rhs, <i33 9, i33 9> 788 %rhs24 = ashr <2 x i33> %shl.rhs, <i33 9, i33 9> 789 %mul = mul <2 x i33> %lhs24, %rhs24 790 ret <2 x i33> %mul 791} 792