1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s 3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s 4 5--- 6name: reg_sequence_ss_vreg 7legalized: true 8tracksRegLiveness: true 9 10body: | 11 bb.0: 12 liveins: $sgpr0, $sgpr1 13 14 ; CHECK-LABEL: name: reg_sequence_ss_vreg 15 ; CHECK: liveins: $sgpr0, $sgpr1 16 ; CHECK-NEXT: {{ $}} 17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 18 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 19 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 20 %0:_(s32) = COPY $sgpr0 21 %1:_(s32) = COPY $sgpr1 22 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 23... 24 25--- 26name: reg_sequence_ss_physreg 27legalized: true 28tracksRegLiveness: true 29 30body: | 31 bb.0: 32 liveins: $sgpr0, $sgpr1 33 34 ; CHECK-LABEL: name: reg_sequence_ss_physreg 35 ; CHECK: liveins: $sgpr0, $sgpr1 36 ; CHECK-NEXT: {{ $}} 37 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1 38 %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1 39... 40 41--- 42name: reg_sequence_sv_vreg 43legalized: true 44tracksRegLiveness: true 45 46body: | 47 bb.0: 48 liveins: $sgpr0, $vgpr0 49 50 ; CHECK-LABEL: name: reg_sequence_sv_vreg 51 ; CHECK: liveins: $sgpr0, $vgpr0 52 ; CHECK-NEXT: {{ $}} 53 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 54 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 55 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 56 %0:_(s32) = COPY $sgpr0 57 %1:_(s32) = COPY $vgpr0 58 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 59... 60 61--- 62name: reg_sequence_sv_physreg 63legalized: true 64tracksRegLiveness: true 65 66body: | 67 bb.0: 68 liveins: $sgpr0, $vgpr0 69 70 ; CHECK-LABEL: name: reg_sequence_sv_physreg 71 ; CHECK: liveins: $sgpr0, $vgpr0 72 ; CHECK-NEXT: {{ $}} 73 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1 74 %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1 75... 76 77--- 78name: reg_sequence_vs_vreg 79legalized: true 80tracksRegLiveness: true 81 82body: | 83 bb.0: 84 liveins: $vgpr0, $sgpr0 85 86 ; CHECK-LABEL: name: reg_sequence_vs_vreg 87 ; CHECK: liveins: $vgpr0, $sgpr0 88 ; CHECK-NEXT: {{ $}} 89 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 90 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 91 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 92 %0:_(s32) = COPY $vgpr0 93 %1:_(s32) = COPY $sgpr0 94 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 95... 96 97--- 98name: reg_sequence_vs_physreg 99legalized: true 100tracksRegLiveness: true 101 102body: | 103 bb.0: 104 liveins: $vgpr0, $sgpr0 105 106 ; CHECK-LABEL: name: reg_sequence_vs_physreg 107 ; CHECK: liveins: $vgpr0, $sgpr0 108 ; CHECK-NEXT: {{ $}} 109 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1 110 %0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1 111... 112 113--- 114name: reg_sequence_vv_vreg 115legalized: true 116tracksRegLiveness: true 117 118body: | 119 bb.0: 120 liveins: $vgpr0, $vgpr1 121 122 ; CHECK-LABEL: name: reg_sequence_vv_vreg 123 ; CHECK: liveins: $vgpr0, $vgpr1 124 ; CHECK-NEXT: {{ $}} 125 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 126 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 127 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 128 %0:_(s32) = COPY $vgpr0 129 %1:_(s32) = COPY $vgpr1 130 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 131... 132 133--- 134name: reg_sequence_vv_physreg 135legalized: true 136tracksRegLiveness: true 137 138body: | 139 bb.0: 140 liveins: $vgpr0, $vgpr1 141 142 ; CHECK-LABEL: name: reg_sequence_vv_physreg 143 ; CHECK: liveins: $vgpr0, $vgpr1 144 ; CHECK-NEXT: {{ $}} 145 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $vgpr1, %subreg.sub1 146 %0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $vgpr1, %subreg.sub1 147... 148 149