xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir (revision 87503fa51c8d726510d48e707a7d2885a5b5936c) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
3# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
4
5---
6name: build_vector_v2s32_ss
7legalized: true
8
9body: |
10  bb.0:
11    liveins: $sgpr0, $sgpr1
12    ; CHECK-LABEL: name: build_vector_v2s32_ss
13    ; CHECK: liveins: $sgpr0, $sgpr1
14    ; CHECK-NEXT: {{  $}}
15    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
16    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
17    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
18    %0:_(s32) = COPY $sgpr0
19    %1:_(s32) = COPY $sgpr1
20    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
21...
22
23---
24name: build_vector_v2s32_sv
25legalized: true
26
27body: |
28  bb.0:
29    liveins: $sgpr0, $vgpr0
30    ; CHECK-LABEL: name: build_vector_v2s32_sv
31    ; CHECK: liveins: $sgpr0, $vgpr0
32    ; CHECK-NEXT: {{  $}}
33    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
34    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
35    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
36    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
37    %0:_(s32) = COPY $sgpr0
38    %1:_(s32) = COPY $vgpr0
39    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
40...
41
42---
43name: build_vector_v2s32_vs
44legalized: true
45
46body: |
47  bb.0:
48    liveins: $vgpr0, $sgpr0
49    ; CHECK-LABEL: name: build_vector_v2s32_vs
50    ; CHECK: liveins: $vgpr0, $sgpr0
51    ; CHECK-NEXT: {{  $}}
52    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
53    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
54    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
55    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY2]](s32)
56    %0:_(s32) = COPY $vgpr0
57    %1:_(s32) = COPY $sgpr0
58    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
59...
60
61---
62name: build_vector_v2s32_vv
63legalized: true
64
65body: |
66  bb.0:
67    liveins: $vgpr0, $vgpr1
68    ; CHECK-LABEL: name: build_vector_v2s32_vv
69    ; CHECK: liveins: $vgpr0, $vgpr1
70    ; CHECK-NEXT: {{  $}}
71    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
72    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
73    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
74    %0:_(s32) = COPY $vgpr0
75    %1:_(s32) = COPY $vgpr1
76    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
77...
78
79---
80name: build_vector_v2s32_aa
81tracksRegLiveness: true
82legalized: true
83
84body: |
85  bb.0:
86    liveins: $agpr0, $agpr1
87
88    ; CHECK-LABEL: name: build_vector_v2s32_aa
89    ; CHECK: liveins: $agpr0, $agpr1
90    ; CHECK-NEXT: {{  $}}
91    ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
92    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
93    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:agpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
94    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
95    %0:_(s32) = COPY $agpr0
96    %1:_(s32) = COPY $agpr1
97    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
98    S_ENDPGM 0, implicit %2
99...
100
101---
102name: build_vector_v2s32_va
103tracksRegLiveness: true
104legalized: true
105
106body: |
107  bb.0:
108    liveins: $vgpr0, $agpr0
109
110    ; CHECK-LABEL: name: build_vector_v2s32_va
111    ; CHECK: liveins: $vgpr0, $agpr0
112    ; CHECK-NEXT: {{  $}}
113    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
114    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
115    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
116    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY2]](s32)
117    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
118    %0:_(s32) = COPY $vgpr0
119    %1:_(s32) = COPY $agpr0
120    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
121    S_ENDPGM 0, implicit %2
122...
123
124---
125name: build_vector_v2s32_av
126tracksRegLiveness: true
127legalized: true
128
129body: |
130  bb.0:
131    liveins: $vgpr0, $agpr0
132
133    ; CHECK-LABEL: name: build_vector_v2s32_av
134    ; CHECK: liveins: $vgpr0, $agpr0
135    ; CHECK-NEXT: {{  $}}
136    ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
137    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
138    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
139    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
140    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
141    %0:_(s32) = COPY $agpr0
142    %1:_(s32) = COPY $vgpr0
143    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
144    S_ENDPGM 0, implicit %2
145...
146
147---
148name: build_vector_v2s32_sa
149tracksRegLiveness: true
150legalized: true
151
152body: |
153  bb.0:
154    liveins: $sgpr0, $agpr0
155
156    ; CHECK-LABEL: name: build_vector_v2s32_sa
157    ; CHECK: liveins: $sgpr0, $agpr0
158    ; CHECK-NEXT: {{  $}}
159    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
160    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
161    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
162    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
163    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
164    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
165    %0:_(s32) = COPY $sgpr0
166    %1:_(s32) = COPY $agpr0
167    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
168    S_ENDPGM 0, implicit %2
169...
170
171---
172name: build_vector_v2s32_as
173tracksRegLiveness: true
174legalized: true
175
176body: |
177  bb.0:
178    liveins: $sgpr0, $agpr0
179
180    ; CHECK-LABEL: name: build_vector_v2s32_as
181    ; CHECK: liveins: $sgpr0, $agpr0
182    ; CHECK-NEXT: {{  $}}
183    ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
184    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
185    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
186    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
187    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
188    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
189    %0:_(s32) = COPY $agpr0
190    %1:_(s32) = COPY $sgpr0
191    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
192    S_ENDPGM 0, implicit %2
193...
194
195---
196name: build_vector_v3s32_aaa
197tracksRegLiveness: true
198legalized: true
199
200body: |
201  bb.0:
202    liveins: $agpr0, $agpr1, $agpr2
203
204    ; CHECK-LABEL: name: build_vector_v3s32_aaa
205    ; CHECK: liveins: $agpr0, $agpr1, $agpr2
206    ; CHECK-NEXT: {{  $}}
207    ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
208    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
209    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
210    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:agpr(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
211    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>)
212    %0:_(s32) = COPY $agpr0
213    %1:_(s32) = COPY $agpr1
214    %2:_(s32) = COPY $agpr2
215    %3:_(<3 x s32>) = G_BUILD_VECTOR %0, %1, %2
216    S_ENDPGM 0, implicit %3
217...
218
219---
220name: build_vector_v4s32_aaaa
221tracksRegLiveness: true
222legalized: true
223
224body: |
225  bb.0:
226    liveins: $agpr0, $agpr1, $agpr2
227
228    ; CHECK-LABEL: name: build_vector_v4s32_aaaa
229    ; CHECK: liveins: $agpr0, $agpr1, $agpr2
230    ; CHECK-NEXT: {{  $}}
231    ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
232    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
233    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
234    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:agpr(s32) = COPY $agpr2
235    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:agpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
236    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>)
237    %0:_(s32) = COPY $agpr0
238    %1:_(s32) = COPY $agpr1
239    %2:_(s32) = COPY $agpr2
240    %3:_(s32) = COPY $agpr2
241    %4:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3
242    S_ENDPGM 0, implicit %4
243...
244
245---
246name: build_vector_v8s32_aaaaaaaa
247tracksRegLiveness: true
248legalized: true
249
250body: |
251  bb.0:
252    liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7
253
254    ; CHECK-LABEL: name: build_vector_v8s32_aaaaaaaa
255    ; CHECK: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7
256    ; CHECK-NEXT: {{  $}}
257    ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
258    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
259    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
260    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:agpr(s32) = COPY $agpr3
261    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:agpr(s32) = COPY $agpr4
262    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:agpr(s32) = COPY $agpr5
263    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:agpr(s32) = COPY $agpr6
264    ; CHECK-NEXT: [[COPY7:%[0-9]+]]:agpr(s32) = COPY $agpr7
265    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:agpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
266    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>)
267    %0:_(s32) = COPY $agpr0
268    %1:_(s32) = COPY $agpr1
269    %2:_(s32) = COPY $agpr2
270    %3:_(s32) = COPY $agpr3
271    %4:_(s32) = COPY $agpr4
272    %5:_(s32) = COPY $agpr5
273    %6:_(s32) = COPY $agpr6
274    %7:_(s32) = COPY $agpr7
275    %8:_(<8 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3, %4, %5, %6, %7
276    S_ENDPGM 0, implicit %8
277...
278
279---
280name: build_vector_v16s32_aaaaaaaaaaaaaaaa
281tracksRegLiveness: true
282legalized: true
283
284body: |
285  bb.0:
286    liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15
287
288    ; CHECK-LABEL: name: build_vector_v16s32_aaaaaaaaaaaaaaaa
289    ; CHECK: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15
290    ; CHECK-NEXT: {{  $}}
291    ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
292    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
293    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
294    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:agpr(s32) = COPY $agpr3
295    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:agpr(s32) = COPY $agpr4
296    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:agpr(s32) = COPY $agpr5
297    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:agpr(s32) = COPY $agpr6
298    ; CHECK-NEXT: [[COPY7:%[0-9]+]]:agpr(s32) = COPY $agpr7
299    ; CHECK-NEXT: [[COPY8:%[0-9]+]]:agpr(s32) = COPY $agpr8
300    ; CHECK-NEXT: [[COPY9:%[0-9]+]]:agpr(s32) = COPY $agpr9
301    ; CHECK-NEXT: [[COPY10:%[0-9]+]]:agpr(s32) = COPY $agpr10
302    ; CHECK-NEXT: [[COPY11:%[0-9]+]]:agpr(s32) = COPY $agpr11
303    ; CHECK-NEXT: [[COPY12:%[0-9]+]]:agpr(s32) = COPY $agpr12
304    ; CHECK-NEXT: [[COPY13:%[0-9]+]]:agpr(s32) = COPY $agpr13
305    ; CHECK-NEXT: [[COPY14:%[0-9]+]]:agpr(s32) = COPY $agpr14
306    ; CHECK-NEXT: [[COPY15:%[0-9]+]]:agpr(s32) = COPY $agpr15
307    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:agpr(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
308    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<16 x s32>)
309    %0:_(s32) = COPY $agpr0
310    %1:_(s32) = COPY $agpr1
311    %2:_(s32) = COPY $agpr2
312    %3:_(s32) = COPY $agpr3
313    %4:_(s32) = COPY $agpr4
314    %5:_(s32) = COPY $agpr5
315    %6:_(s32) = COPY $agpr6
316    %7:_(s32) = COPY $agpr7
317    %8:_(s32) = COPY $agpr8
318    %9:_(s32) = COPY $agpr9
319    %10:_(s32) = COPY $agpr10
320    %11:_(s32) = COPY $agpr11
321    %12:_(s32) = COPY $agpr12
322    %13:_(s32) = COPY $agpr13
323    %14:_(s32) = COPY $agpr14
324    %15:_(s32) = COPY $agpr15
325    %16:_(<16 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15
326    S_ENDPGM 0, implicit %16
327...
328