xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir (revision 87503fa51c8d726510d48e707a7d2885a5b5936c) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s
3
4---
5name:            assert_zext_vgpr
6alignment:       4
7legalized:       true
8tracksRegLiveness: true
9body:             |
10  bb.0:
11    liveins: $vgpr0
12
13    ; CHECK-LABEL: name: assert_zext_vgpr
14    ; CHECK: liveins: $vgpr0
15    ; CHECK-NEXT: {{  $}}
16    ; CHECK-NEXT: %copy:vgpr(s32) = COPY $vgpr0
17    ; CHECK-NEXT: %assert_zext:vgpr(s32) = G_ASSERT_ZEXT %copy, 4
18    ; CHECK-NEXT: S_ENDPGM 0, implicit %assert_zext(s32)
19    %copy:_(s32) = COPY $vgpr0
20    %assert_zext:_(s32) = G_ASSERT_ZEXT %copy, 4
21    S_ENDPGM 0, implicit %assert_zext
22...
23
24---
25name:            assert_zext_sgpr
26alignment:       4
27legalized:       true
28tracksRegLiveness: true
29body:             |
30  bb.0:
31    liveins: $sgpr8
32
33    ; CHECK-LABEL: name: assert_zext_sgpr
34    ; CHECK: liveins: $sgpr8
35    ; CHECK-NEXT: {{  $}}
36    ; CHECK-NEXT: %copy:sgpr(s32) = COPY $sgpr8
37    ; CHECK-NEXT: %assert_zext:sgpr(s32) = G_ASSERT_ZEXT %copy, 4
38    ; CHECK-NEXT: S_ENDPGM 0, implicit %assert_zext(s32)
39    %copy:_(s32) = COPY $sgpr8
40    %assert_zext:_(s32) = G_ASSERT_ZEXT %copy, 4
41    S_ENDPGM 0, implicit %assert_zext
42...
43
44---
45name:            assert_zext_agpr
46alignment:       4
47legalized:       true
48tracksRegLiveness: true
49body:             |
50  bb.0:
51    liveins: $agpr0
52
53    ; CHECK-LABEL: name: assert_zext_agpr
54    ; CHECK: liveins: $agpr0
55    ; CHECK-NEXT: {{  $}}
56    ; CHECK-NEXT: %copy:agpr(s32) = COPY $agpr0
57    ; CHECK-NEXT: %assert_zext:agpr(s32) = G_ASSERT_ZEXT %copy, 4
58    ; CHECK-NEXT: S_ENDPGM 0, implicit %assert_zext(s32)
59    %copy:_(s32) = COPY $agpr0
60    %assert_zext:_(s32) = G_ASSERT_ZEXT %copy, 4
61    S_ENDPGM 0, implicit %assert_zext
62...
63
64---
65name:            assert_zext_vgpr_regclass
66alignment:       4
67legalized:       true
68tracksRegLiveness: true
69body:             |
70  bb.0:
71    liveins: $vgpr0
72
73    ; CHECK-LABEL: name: assert_zext_vgpr_regclass
74    ; CHECK: liveins: $vgpr0
75    ; CHECK-NEXT: {{  $}}
76    ; CHECK-NEXT: %copy:vgpr_32(s32) = COPY $vgpr0
77    ; CHECK-NEXT: %assert_zext:vgpr(s32) = G_ASSERT_ZEXT %copy, 4
78    ; CHECK-NEXT: S_ENDPGM 0, implicit %assert_zext(s32)
79    %copy:vgpr_32(s32) = COPY $vgpr0
80    %assert_zext:_(s32) = G_ASSERT_ZEXT %copy, 4
81    S_ENDPGM 0, implicit %assert_zext
82...
83
84---
85name:            assert_zext_sgpr_regcllass
86alignment:       4
87legalized:       true
88tracksRegLiveness: true
89body:             |
90  bb.0:
91    liveins: $sgpr8
92
93    ; CHECK-LABEL: name: assert_zext_sgpr_regcllass
94    ; CHECK: liveins: $sgpr8
95    ; CHECK-NEXT: {{  $}}
96    ; CHECK-NEXT: %copy:sgpr_32(s32) = COPY $sgpr8
97    ; CHECK-NEXT: %assert_zext:sgpr(s32) = G_ASSERT_ZEXT %copy, 4
98    ; CHECK-NEXT: S_ENDPGM 0, implicit %assert_zext(s32)
99    %copy:sgpr_32(s32) = COPY $sgpr8
100    %assert_zext:_(s32) = G_ASSERT_ZEXT %copy, 4
101    S_ENDPGM 0, implicit %assert_zext
102...
103