xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir (revision 87503fa51c8d726510d48e707a7d2885a5b5936c) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
4
5---
6name: add_v2s16_ss
7legalized: true
8
9body: |
10  bb.0:
11    liveins: $sgpr0, $sgpr1
12    ; CHECK-LABEL: name: add_v2s16_ss
13    ; CHECK: liveins: $sgpr0, $sgpr1
14    ; CHECK-NEXT: {{  $}}
15    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
16    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
17    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
18    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
19    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)
20    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
21    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
22    ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
23    ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[BITCAST]], [[BITCAST1]]
24    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:sgpr(s32) = G_ADD [[LSHR]], [[LSHR1]]
25    ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ADD]](s32), [[ADD1]](s32)
26    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
27    %0:_(<2 x s16>) = COPY $sgpr0
28    %1:_(<2 x s16>) = COPY $sgpr1
29    %2:_(<2 x s16>) = G_ADD %0, %1
30    S_ENDPGM 0, implicit %2
31...
32
33---
34name: add_v2s16_sv
35legalized: true
36
37body: |
38  bb.0:
39    liveins: $sgpr0, $vgpr0
40    ; CHECK-LABEL: name: add_v2s16_sv
41    ; CHECK: liveins: $sgpr0, $vgpr0
42    ; CHECK-NEXT: {{  $}}
43    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
44    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
45    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
46    ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY2]], [[COPY1]]
47    ; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](<2 x s16>)
48    %0:_(<2 x s16>) = COPY $sgpr0
49    %1:_(<2 x s16>) = COPY $vgpr0
50    %2:_(<2 x s16>) = G_ADD %0, %1
51    S_ENDPGM 0, implicit %2
52...
53
54---
55name: add_v2s16_vs
56legalized: true
57
58body: |
59  bb.0:
60    liveins: $sgpr0, $vgpr0
61    ; CHECK-LABEL: name: add_v2s16_vs
62    ; CHECK: liveins: $sgpr0, $vgpr0
63    ; CHECK-NEXT: {{  $}}
64    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
65    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
66    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
67    ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY]], [[COPY2]]
68    %0:_(<2 x s16>) = COPY $vgpr0
69    %1:_(<2 x s16>) = COPY $sgpr0
70    %2:_(<2 x s16>) = G_ADD %0, %1
71...
72
73---
74name: add_v2s16_vv
75legalized: true
76
77body: |
78  bb.0:
79    liveins: $vgpr0, $vgpr1
80    ; CHECK-LABEL: name: add_v2s16_vv
81    ; CHECK: liveins: $vgpr0, $vgpr1
82    ; CHECK-NEXT: {{  $}}
83    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
84    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
85    ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY]], [[COPY1]]
86    ; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](<2 x s16>)
87    %0:_(<2 x s16>) = COPY $vgpr0
88    %1:_(<2 x s16>) = COPY $vgpr1
89    %2:_(<2 x s16>) = G_ADD %0, %1
90    S_ENDPGM 0, implicit %2
91...
92