1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX906 %s 3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10PLUS,GFX10 %s 4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10PLUS,GFX10 %s 5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10PLUS,GFX11 %s 6 7define i32 @v_udot4(i32 %a, i32 %b, i32 %c) { 8; GFX906-LABEL: v_udot4: 9; GFX906: ; %bb.0: 10; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 12; GFX906-NEXT: s_setpc_b64 s[30:31] 13; 14; GFX10PLUS-LABEL: v_udot4: 15; GFX10PLUS: ; %bb.0: 16; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 17; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 18; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 19 %r = call i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 false) 20 ret i32 %r 21} 22 23define i32 @v_udot4_clamp(i32 %a, i32 %b, i32 %c) { 24; GFX906-LABEL: v_udot4_clamp: 25; GFX906: ; %bb.0: 26; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 27; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp 28; GFX906-NEXT: s_setpc_b64 s[30:31] 29; 30; GFX10PLUS-LABEL: v_udot4_clamp: 31; GFX10PLUS: ; %bb.0: 32; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 33; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp 34; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 35 %r = call i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 true) 36 ret i32 %r 37} 38 39; FIXME: bitcast should not expand 40define i32 @v_udot4_cast_v4i8(<4 x i8> %a, <4 x i8> %b, i32 %c) { 41; GFX906-LABEL: v_udot4_cast_v4i8: 42; GFX906: ; %bb.0: 43; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 44; GFX906-NEXT: v_mov_b32_e32 v10, 8 45; GFX906-NEXT: v_mov_b32_e32 v9, 0xff 46; GFX906-NEXT: v_lshlrev_b32_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 47; GFX906-NEXT: v_and_or_b32 v0, v0, v9, v1 48; GFX906-NEXT: v_and_b32_e32 v1, 0xff, v2 49; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v3 50; GFX906-NEXT: v_lshlrev_b32_e32 v1, 16, v1 51; GFX906-NEXT: v_lshlrev_b32_e32 v2, 24, v2 52; GFX906-NEXT: v_or3_b32 v0, v0, v1, v2 53; GFX906-NEXT: v_lshlrev_b32_sdwa v1, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 54; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v6 55; GFX906-NEXT: v_and_b32_e32 v3, 0xff, v7 56; GFX906-NEXT: v_and_or_b32 v1, v4, v9, v1 57; GFX906-NEXT: v_lshlrev_b32_e32 v2, 16, v2 58; GFX906-NEXT: v_lshlrev_b32_e32 v3, 24, v3 59; GFX906-NEXT: v_or3_b32 v1, v1, v2, v3 60; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v8 61; GFX906-NEXT: s_setpc_b64 s[30:31] 62; 63; GFX10-LABEL: v_udot4_cast_v4i8: 64; GFX10: ; %bb.0: 65; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 66; GFX10-NEXT: v_mov_b32_e32 v9, 8 67; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 68; GFX10-NEXT: v_and_or_b32 v0, 0xff, v0, v1 69; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v2 70; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v3 71; GFX10-NEXT: v_lshlrev_b32_sdwa v3, v9, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 72; GFX10-NEXT: v_and_b32_e32 v5, 0xff, v6 73; GFX10-NEXT: v_and_b32_e32 v6, 0xff, v7 74; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 75; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2 76; GFX10-NEXT: v_and_or_b32 v3, 0xff, v4, v3 77; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v5 78; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v6 79; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 80; GFX10-NEXT: v_or3_b32 v1, v3, v4, v5 81; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v8 82; GFX10-NEXT: s_setpc_b64 s[30:31] 83; 84; GFX11-LABEL: v_udot4_cast_v4i8: 85; GFX11: ; %bb.0: 86; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 87; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1 88; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5 89; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2 90; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3 91; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v1 92; GFX11-NEXT: v_lshlrev_b32_e32 v5, 8, v5 93; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2 94; GFX11-NEXT: v_lshlrev_b32_e32 v3, 24, v3 95; GFX11-NEXT: v_and_or_b32 v0, 0xff, v0, v1 96; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v6 97; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v7 98; GFX11-NEXT: v_and_or_b32 v4, 0xff, v4, v5 99; GFX11-NEXT: v_or3_b32 v0, v0, v2, v3 100; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 101; GFX11-NEXT: v_lshlrev_b32_e32 v5, 24, v6 102; GFX11-NEXT: v_or3_b32 v1, v4, v1, v5 103; GFX11-NEXT: v_dot4_u32_u8 v0, v0, v1, v8 104; GFX11-NEXT: s_setpc_b64 s[30:31] 105 %a.cast = bitcast <4 x i8> %a to i32 106 %b.cast = bitcast <4 x i8> %b to i32 107 %r = call i32 @llvm.amdgcn.udot4(i32 %a.cast, i32 %b.cast, i32 %c, i1 false) 108 ret i32 %r 109} 110 111define i32 @v_udot4_fnegf32_a(float %a, i32 %b, i32 %c) { 112; GFX906-LABEL: v_udot4_fnegf32_a: 113; GFX906: ; %bb.0: 114; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 115; GFX906-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 116; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 117; GFX906-NEXT: s_setpc_b64 s[30:31] 118; 119; GFX10PLUS-LABEL: v_udot4_fnegf32_a: 120; GFX10PLUS: ; %bb.0: 121; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 122; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 123; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 124; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 125 %neg.a = fneg float %a 126 %cast.neg.a = bitcast float %neg.a to i32 127 %r = call i32 @llvm.amdgcn.udot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false) 128 ret i32 %r 129} 130 131define i32 @v_udot4_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) { 132; GFX906-LABEL: v_udot4_fnegv2f16_a: 133; GFX906: ; %bb.0: 134; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 135; GFX906-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 136; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 137; GFX906-NEXT: s_setpc_b64 s[30:31] 138; 139; GFX10PLUS-LABEL: v_udot4_fnegv2f16_a: 140; GFX10PLUS: ; %bb.0: 141; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 142; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 143; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 144; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 145 %neg.a = fneg <2 x half> %a 146 %cast.neg.a = bitcast <2 x half> %neg.a to i32 147 %r = call i32 @llvm.amdgcn.udot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false) 148 ret i32 %r 149} 150 151declare i32 @llvm.amdgcn.udot4(i32, i32, i32, i1 immarg) #0 152 153attributes #0 = { nounwind readnone speculatable } 154