1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -verify-machineinstrs -global-isel-abort=2 %s -o - | FileCheck %s 3 4--- 5name: test_phi_s32 6tracksRegLiveness: true 7 8body: | 9 ; CHECK-LABEL: name: test_phi_s32 10 ; CHECK: bb.0: 11 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 12 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 13 ; CHECK-NEXT: {{ $}} 14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 15 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 16 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 17 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 18 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 19 ; CHECK-NEXT: G_BR %bb.2 20 ; CHECK-NEXT: {{ $}} 21 ; CHECK-NEXT: bb.1: 22 ; CHECK-NEXT: successors: %bb.2(0x80000000) 23 ; CHECK-NEXT: {{ $}} 24 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]] 25 ; CHECK-NEXT: G_BR %bb.2 26 ; CHECK-NEXT: {{ $}} 27 ; CHECK-NEXT: bb.2: 28 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY]](s32), %bb.0, [[ADD]](s32), %bb.1 29 ; CHECK-NEXT: $vgpr0 = COPY [[PHI]](s32) 30 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 31 bb.0: 32 successors: %bb.1, %bb.2 33 liveins: $vgpr0, $vgpr1 34 35 %0:_(s32) = COPY $vgpr0 36 %1:_(s32) = COPY $vgpr1 37 %2:_(s32) = G_CONSTANT i32 0 38 %3:_(s1) = G_ICMP intpred(eq), %1, %2 39 G_BRCOND %3, %bb.1 40 G_BR %bb.2 41 42 bb.1: 43 successors: %bb.2 44 45 %4:_(s32) = G_ADD %0, %0 46 G_BR %bb.2 47 48 bb.2: 49 %5:_(s32) = G_PHI %0, %bb.0, %4, %bb.1 50 $vgpr0 = COPY %5 51 S_SETPC_B64 undef $sgpr30_sgpr31 52 53... 54--- 55name: test_phi_v2s16 56tracksRegLiveness: true 57 58body: | 59 ; CHECK-LABEL: name: test_phi_v2s16 60 ; CHECK: bb.0: 61 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 62 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 63 ; CHECK-NEXT: {{ $}} 64 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 65 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 66 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 67 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 68 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 69 ; CHECK-NEXT: G_BR %bb.2 70 ; CHECK-NEXT: {{ $}} 71 ; CHECK-NEXT: bb.1: 72 ; CHECK-NEXT: successors: %bb.2(0x80000000) 73 ; CHECK-NEXT: {{ $}} 74 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) 75 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 76 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32) 77 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) 78 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32) 79 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST1]] 80 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR1]] 81 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 82 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]] 83 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C2]] 84 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32) 85 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] 86 ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) 87 ; CHECK-NEXT: G_BR %bb.2 88 ; CHECK-NEXT: {{ $}} 89 ; CHECK-NEXT: bb.2: 90 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<2 x s16>) = G_PHI [[COPY]](<2 x s16>), %bb.0, [[BITCAST2]](<2 x s16>), %bb.1 91 ; CHECK-NEXT: $vgpr0 = COPY [[PHI]](<2 x s16>) 92 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 93 bb.0: 94 successors: %bb.1, %bb.2 95 liveins: $vgpr0, $vgpr1 96 97 %0:_(<2 x s16>) = COPY $vgpr0 98 %1:_(s32) = COPY $vgpr1 99 %2:_(s32) = G_CONSTANT i32 0 100 %3:_(s1) = G_ICMP intpred(eq), %1, %2 101 G_BRCOND %3, %bb.1 102 G_BR %bb.2 103 104 bb.1: 105 successors: %bb.2 106 107 %5:_(<2 x s16>) = G_ADD %0, %0 108 G_BR %bb.2 109 110 bb.2: 111 %6:_(<2 x s16>) = G_PHI %0, %bb.0, %5, %bb.1 112 $vgpr0 = COPY %6 113 S_SETPC_B64 undef $sgpr30_sgpr31 114... 115 116--- 117name: test_phi_v3s16 118tracksRegLiveness: true 119 120body: | 121 ; CHECK-LABEL: name: test_phi_v3s16 122 ; CHECK: bb.0: 123 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 124 ; CHECK-NEXT: liveins: $vgpr0_vgpr1, $vgpr2 125 ; CHECK-NEXT: {{ $}} 126 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 127 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 128 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 129 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 130 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) 131 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) 132 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 133 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32) 134 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) 135 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 136 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]] 137 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C1]](s32) 138 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] 139 ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) 140 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST2]](<2 x s16>) 141 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 142 ; CHECK-NEXT: G_BR %bb.2 143 ; CHECK-NEXT: {{ $}} 144 ; CHECK-NEXT: bb.1: 145 ; CHECK-NEXT: successors: %bb.2(0x80000000) 146 ; CHECK-NEXT: {{ $}} 147 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST]] 148 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR]] 149 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[BITCAST1]], [[BITCAST1]] 150 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 151 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]] 152 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C3]] 153 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 154 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C4]](s32) 155 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]] 156 ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) 157 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C3]] 158 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 159 ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C5]], [[C4]](s32) 160 ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]] 161 ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32) 162 ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>) 163 ; CHECK-NEXT: G_BR %bb.2 164 ; CHECK-NEXT: {{ $}} 165 ; CHECK-NEXT: bb.2: 166 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<4 x s16>) = G_PHI [[CONCAT_VECTORS]](<4 x s16>), %bb.0, [[CONCAT_VECTORS1]](<4 x s16>), %bb.1 167 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[PHI]](<4 x s16>) 168 ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>) 169 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 170 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF 171 ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>) 172 ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>) 173 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C6]](s32) 174 ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>) 175 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 176 ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C7]] 177 ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C7]] 178 ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32) 179 ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]] 180 ; CHECK-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32) 181 ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C7]] 182 ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32) 183 ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL4]] 184 ; CHECK-NEXT: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32) 185 ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV2]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BITCAST9]](<2 x s16>) 186 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>) 187 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 188 bb.0: 189 successors: %bb.1, %bb.2 190 liveins: $vgpr0_vgpr1, $vgpr2 191 192 %0:_(<4 x s16>) = COPY $vgpr0_vgpr1 193 %1:_(s32) = COPY $vgpr2 194 %2:_(s32) = G_CONSTANT i32 0 195 %3:_(s1) = G_ICMP intpred(eq), %1, %2 196 %4:_(<3 x s16>) = G_EXTRACT %0, 0 197 G_BRCOND %3, %bb.1 198 G_BR %bb.2 199 200 bb.1: 201 successors: %bb.2 202 203 %5:_(<3 x s16>) = G_ADD %4, %4 204 G_BR %bb.2 205 206 bb.2: 207 %6:_(<3 x s16>) = G_PHI %4, %bb.0, %5, %bb.1 208 %7:_(<3 x s16>) = G_IMPLICIT_DEF 209 %8:_(<6 x s16>) = G_CONCAT_VECTORS %6, %7 210 $vgpr0_vgpr1_vgpr2 = COPY %8 211 S_SETPC_B64 undef $sgpr30_sgpr31 212... 213 214--- 215 216name: test_phi_v4s16 217tracksRegLiveness: true 218 219body: | 220 ; CHECK-LABEL: name: test_phi_v4s16 221 ; CHECK: bb.0: 222 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 223 ; CHECK-NEXT: liveins: $vgpr0_vgpr1, $vgpr2 224 ; CHECK-NEXT: {{ $}} 225 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 226 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 227 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 228 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 229 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 230 ; CHECK-NEXT: G_BR %bb.2 231 ; CHECK-NEXT: {{ $}} 232 ; CHECK-NEXT: bb.1: 233 ; CHECK-NEXT: successors: %bb.2(0x80000000) 234 ; CHECK-NEXT: {{ $}} 235 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) 236 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) 237 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 238 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32) 239 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) 240 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32) 241 ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) 242 ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32) 243 ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) 244 ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32) 245 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST2]] 246 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR2]] 247 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[BITCAST1]], [[BITCAST3]] 248 ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR3]] 249 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 250 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]] 251 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C2]] 252 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32) 253 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] 254 ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) 255 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C2]] 256 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C2]] 257 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32) 258 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]] 259 ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) 260 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>) 261 ; CHECK-NEXT: G_BR %bb.2 262 ; CHECK-NEXT: {{ $}} 263 ; CHECK-NEXT: bb.2: 264 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<4 x s16>) = G_PHI [[COPY]](<4 x s16>), %bb.0, [[CONCAT_VECTORS]](<4 x s16>), %bb.1 265 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[PHI]](<4 x s16>) 266 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 267 bb.0: 268 successors: %bb.1, %bb.2 269 liveins: $vgpr0_vgpr1, $vgpr2 270 271 %0:_(<4 x s16>) = COPY $vgpr0_vgpr1 272 %1:_(s32) = COPY $vgpr2 273 %2:_(s32) = G_CONSTANT i32 0 274 %3:_(s1) = G_ICMP intpred(eq), %1, %2 275 G_BRCOND %3, %bb.1 276 G_BR %bb.2 277 278 bb.1: 279 successors: %bb.2 280 281 %4:_(<4 x s16>) = G_ADD %0, %0 282 G_BR %bb.2 283 284 bb.2: 285 %5:_(<4 x s16>) = G_PHI %0, %bb.0, %4, %bb.1 286 $vgpr0_vgpr1 = COPY %5 287 S_SETPC_B64 undef $sgpr30_sgpr31 288 289... 290--- 291name: test_phi_v2s32 292tracksRegLiveness: true 293 294body: | 295 ; CHECK-LABEL: name: test_phi_v2s32 296 ; CHECK: bb.0: 297 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 298 ; CHECK-NEXT: liveins: $vgpr0_vgpr1, $vgpr2 299 ; CHECK-NEXT: {{ $}} 300 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 301 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 302 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 303 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 304 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 305 ; CHECK-NEXT: G_BR %bb.2 306 ; CHECK-NEXT: {{ $}} 307 ; CHECK-NEXT: bb.1: 308 ; CHECK-NEXT: successors: %bb.2(0x80000000) 309 ; CHECK-NEXT: {{ $}} 310 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 311 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 312 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV2]] 313 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV3]] 314 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32) 315 ; CHECK-NEXT: G_BR %bb.2 316 ; CHECK-NEXT: {{ $}} 317 ; CHECK-NEXT: bb.2: 318 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<2 x s32>) = G_PHI [[COPY]](<2 x s32>), %bb.0, [[BUILD_VECTOR]](<2 x s32>), %bb.1 319 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[PHI]](<2 x s32>) 320 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 321 bb.0: 322 successors: %bb.1, %bb.2 323 liveins: $vgpr0_vgpr1, $vgpr2 324 325 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 326 %1:_(s32) = COPY $vgpr2 327 %2:_(s32) = G_CONSTANT i32 0 328 %3:_(s1) = G_ICMP intpred(eq), %1, %2 329 G_BRCOND %3, %bb.1 330 G_BR %bb.2 331 332 bb.1: 333 successors: %bb.2 334 335 %4:_(<2 x s32>) = G_ADD %0, %0 336 G_BR %bb.2 337 338 bb.2: 339 %5:_(<2 x s32>) = G_PHI %0, %bb.0, %4, %bb.1 340 $vgpr0_vgpr1 = COPY %5 341 S_SETPC_B64 undef $sgpr30_sgpr31 342 343... 344--- 345name: test_phi_v3s32 346tracksRegLiveness: true 347 348body: | 349 ; CHECK-LABEL: name: test_phi_v3s32 350 ; CHECK: bb.0: 351 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 352 ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3 353 ; CHECK-NEXT: {{ $}} 354 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 355 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3 356 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 357 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 358 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 359 ; CHECK-NEXT: G_BR %bb.2 360 ; CHECK-NEXT: {{ $}} 361 ; CHECK-NEXT: bb.1: 362 ; CHECK-NEXT: successors: %bb.2(0x80000000) 363 ; CHECK-NEXT: {{ $}} 364 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) 365 ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) 366 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV3]] 367 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV4]] 368 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV5]] 369 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32) 370 ; CHECK-NEXT: G_BR %bb.2 371 ; CHECK-NEXT: {{ $}} 372 ; CHECK-NEXT: bb.2: 373 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<3 x s32>) = G_PHI [[COPY]](<3 x s32>), %bb.0, [[BUILD_VECTOR]](<3 x s32>), %bb.1 374 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[PHI]](<3 x s32>) 375 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 376 bb.0: 377 successors: %bb.1, %bb.2 378 liveins: $vgpr0_vgpr1_vgpr2, $vgpr3 379 380 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 381 %1:_(s32) = COPY $vgpr3 382 %2:_(s32) = G_CONSTANT i32 0 383 %3:_(s1) = G_ICMP intpred(eq), %1, %2 384 G_BRCOND %3, %bb.1 385 G_BR %bb.2 386 387 bb.1: 388 successors: %bb.2 389 390 %4:_(<3 x s32>) = G_ADD %0, %0 391 G_BR %bb.2 392 393 bb.2: 394 %5:_(<3 x s32>) = G_PHI %0, %bb.0, %4, %bb.1 395 $vgpr0_vgpr1_vgpr2 = COPY %5 396 S_SETPC_B64 undef $sgpr30_sgpr31 397 398... 399--- 400name: test_phi_v4s32 401tracksRegLiveness: true 402 403body: | 404 ; CHECK-LABEL: name: test_phi_v4s32 405 ; CHECK: bb.0: 406 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 407 ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 408 ; CHECK-NEXT: {{ $}} 409 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 410 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4 411 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 412 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 413 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 414 ; CHECK-NEXT: G_BR %bb.2 415 ; CHECK-NEXT: {{ $}} 416 ; CHECK-NEXT: bb.1: 417 ; CHECK-NEXT: successors: %bb.2(0x80000000) 418 ; CHECK-NEXT: {{ $}} 419 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>) 420 ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>) 421 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV4]] 422 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV5]] 423 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV6]] 424 ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV7]] 425 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32) 426 ; CHECK-NEXT: G_BR %bb.2 427 ; CHECK-NEXT: {{ $}} 428 ; CHECK-NEXT: bb.2: 429 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<4 x s32>) = G_PHI [[COPY]](<4 x s32>), %bb.0, [[BUILD_VECTOR]](<4 x s32>), %bb.1 430 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[PHI]](<4 x s32>) 431 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 432 bb.0: 433 successors: %bb.1, %bb.2 434 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 435 436 %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 437 %1:_(s32) = COPY $vgpr4 438 %2:_(s32) = G_CONSTANT i32 0 439 %3:_(s1) = G_ICMP intpred(eq), %1, %2 440 G_BRCOND %3, %bb.1 441 G_BR %bb.2 442 443 bb.1: 444 successors: %bb.2 445 446 %4:_(<4 x s32>) = G_ADD %0, %0 447 G_BR %bb.2 448 449 bb.2: 450 %5:_(<4 x s32>) = G_PHI %0, %bb.0, %4, %bb.1 451 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5 452 S_SETPC_B64 undef $sgpr30_sgpr31 453 454... 455--- 456name: test_phi_v8s32 457tracksRegLiveness: true 458 459body: | 460 ; CHECK-LABEL: name: test_phi_v8s32 461 ; CHECK: bb.0: 462 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 463 ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8 464 ; CHECK-NEXT: {{ $}} 465 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 466 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8 467 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 468 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 469 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 470 ; CHECK-NEXT: G_BR %bb.2 471 ; CHECK-NEXT: {{ $}} 472 ; CHECK-NEXT: bb.1: 473 ; CHECK-NEXT: successors: %bb.2(0x80000000) 474 ; CHECK-NEXT: {{ $}} 475 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s32>) 476 ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s32>) 477 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV8]] 478 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV9]] 479 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV10]] 480 ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV11]] 481 ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UV4]], [[UV12]] 482 ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[UV13]] 483 ; CHECK-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[UV6]], [[UV14]] 484 ; CHECK-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UV7]], [[UV15]] 485 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s32), [[ADD5]](s32), [[ADD6]](s32), [[ADD7]](s32) 486 ; CHECK-NEXT: G_BR %bb.2 487 ; CHECK-NEXT: {{ $}} 488 ; CHECK-NEXT: bb.2: 489 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<8 x s32>) = G_PHI [[COPY]](<8 x s32>), %bb.0, [[BUILD_VECTOR]](<8 x s32>), %bb.1 490 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[PHI]](<8 x s32>) 491 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 492 bb.0: 493 successors: %bb.1, %bb.2 494 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8 495 496 %0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 497 %1:_(s32) = COPY $vgpr8 498 %2:_(s32) = G_CONSTANT i32 0 499 %3:_(s1) = G_ICMP intpred(eq), %1, %2 500 G_BRCOND %3, %bb.1 501 G_BR %bb.2 502 503 bb.1: 504 successors: %bb.2 505 506 %4:_(<8 x s32>) = G_ADD %0, %0 507 G_BR %bb.2 508 509 bb.2: 510 %5:_(<8 x s32>) = G_PHI %0, %bb.0, %4, %bb.1 511 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %5 512 S_SETPC_B64 undef $sgpr30_sgpr31 513 514... 515--- 516name: test_phi_v16s32 517tracksRegLiveness: true 518 519body: | 520 ; CHECK-LABEL: name: test_phi_v16s32 521 ; CHECK: bb.0: 522 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 523 ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 524 ; CHECK-NEXT: {{ $}} 525 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF 526 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr4 527 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 528 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] 529 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 530 ; CHECK-NEXT: G_BR %bb.2 531 ; CHECK-NEXT: {{ $}} 532 ; CHECK-NEXT: bb.1: 533 ; CHECK-NEXT: successors: %bb.2(0x80000000) 534 ; CHECK-NEXT: {{ $}} 535 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<16 x s32>) 536 ; CHECK-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<16 x s32>) 537 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV16]] 538 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV17]] 539 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV18]] 540 ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV19]] 541 ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UV4]], [[UV20]] 542 ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[UV21]] 543 ; CHECK-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[UV6]], [[UV22]] 544 ; CHECK-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UV7]], [[UV23]] 545 ; CHECK-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UV8]], [[UV24]] 546 ; CHECK-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[UV9]], [[UV25]] 547 ; CHECK-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[UV10]], [[UV26]] 548 ; CHECK-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UV11]], [[UV27]] 549 ; CHECK-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UV12]], [[UV28]] 550 ; CHECK-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[UV13]], [[UV29]] 551 ; CHECK-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[UV14]], [[UV30]] 552 ; CHECK-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UV15]], [[UV31]] 553 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s32), [[ADD5]](s32), [[ADD6]](s32), [[ADD7]](s32), [[ADD8]](s32), [[ADD9]](s32), [[ADD10]](s32), [[ADD11]](s32), [[ADD12]](s32), [[ADD13]](s32), [[ADD14]](s32), [[ADD15]](s32) 554 ; CHECK-NEXT: G_BR %bb.2 555 ; CHECK-NEXT: {{ $}} 556 ; CHECK-NEXT: bb.2: 557 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<16 x s32>) = G_PHI [[DEF]](<16 x s32>), %bb.0, [[BUILD_VECTOR]](<16 x s32>), %bb.1 558 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[PHI]](<16 x s32>) 559 bb.0: 560 successors: %bb.1, %bb.2 561 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 562 563 %0:_(<16 x s32>) = G_IMPLICIT_DEF 564 %1:_(s32) = COPY $vgpr4 565 %2:_(s32) = G_CONSTANT i32 0 566 %3:_(s1) = G_ICMP intpred(eq), %1, %2 567 G_BRCOND %3, %bb.1 568 G_BR %bb.2 569 570 bb.1: 571 successors: %bb.2 572 573 %4:_(<16 x s32>) = G_ADD %0, %0 574 G_BR %bb.2 575 576 bb.2: 577 %5:_(<16 x s32>) = G_PHI %0, %bb.0, %4, %bb.1 578 S_SETPC_B64 undef $sgpr30_sgpr31, implicit %5 579 580... 581 582--- 583name: test_phi_v32s32 584tracksRegLiveness: true 585 586body: | 587 ; CHECK-LABEL: name: test_phi_v32s32 588 ; CHECK: bb.0: 589 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 590 ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 591 ; CHECK-NEXT: {{ $}} 592 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<32 x s32>) = G_IMPLICIT_DEF 593 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr4 594 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 595 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] 596 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 597 ; CHECK-NEXT: G_BR %bb.2 598 ; CHECK-NEXT: {{ $}} 599 ; CHECK-NEXT: bb.1: 600 ; CHECK-NEXT: successors: %bb.2(0x80000000) 601 ; CHECK-NEXT: {{ $}} 602 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<32 x s32>) 603 ; CHECK-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32), [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32), [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32), [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32), [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32), [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32), [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32), [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32), [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32), [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32), [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32), [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32), [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<32 x s32>) 604 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV32]] 605 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV33]] 606 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV34]] 607 ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV35]] 608 ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UV4]], [[UV36]] 609 ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[UV37]] 610 ; CHECK-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[UV6]], [[UV38]] 611 ; CHECK-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UV7]], [[UV39]] 612 ; CHECK-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UV8]], [[UV40]] 613 ; CHECK-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[UV9]], [[UV41]] 614 ; CHECK-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[UV10]], [[UV42]] 615 ; CHECK-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UV11]], [[UV43]] 616 ; CHECK-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UV12]], [[UV44]] 617 ; CHECK-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[UV13]], [[UV45]] 618 ; CHECK-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[UV14]], [[UV46]] 619 ; CHECK-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UV15]], [[UV47]] 620 ; CHECK-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UV16]], [[UV48]] 621 ; CHECK-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[UV17]], [[UV49]] 622 ; CHECK-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[UV18]], [[UV50]] 623 ; CHECK-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[UV19]], [[UV51]] 624 ; CHECK-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[UV20]], [[UV52]] 625 ; CHECK-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[UV21]], [[UV53]] 626 ; CHECK-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[UV22]], [[UV54]] 627 ; CHECK-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UV23]], [[UV55]] 628 ; CHECK-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UV24]], [[UV56]] 629 ; CHECK-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[UV25]], [[UV57]] 630 ; CHECK-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[UV26]], [[UV58]] 631 ; CHECK-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[UV27]], [[UV59]] 632 ; CHECK-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[UV28]], [[UV60]] 633 ; CHECK-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UV29]], [[UV61]] 634 ; CHECK-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[UV30]], [[UV62]] 635 ; CHECK-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UV31]], [[UV63]] 636 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s32), [[ADD5]](s32), [[ADD6]](s32), [[ADD7]](s32), [[ADD8]](s32), [[ADD9]](s32), [[ADD10]](s32), [[ADD11]](s32), [[ADD12]](s32), [[ADD13]](s32), [[ADD14]](s32), [[ADD15]](s32), [[ADD16]](s32), [[ADD17]](s32), [[ADD18]](s32), [[ADD19]](s32), [[ADD20]](s32), [[ADD21]](s32), [[ADD22]](s32), [[ADD23]](s32), [[ADD24]](s32), [[ADD25]](s32), [[ADD26]](s32), [[ADD27]](s32), [[ADD28]](s32), [[ADD29]](s32), [[ADD30]](s32), [[ADD31]](s32) 637 ; CHECK-NEXT: G_BR %bb.2 638 ; CHECK-NEXT: {{ $}} 639 ; CHECK-NEXT: bb.2: 640 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<32 x s32>) = G_PHI [[DEF]](<32 x s32>), %bb.0, [[BUILD_VECTOR]](<32 x s32>), %bb.1 641 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[PHI]](<32 x s32>) 642 bb.0: 643 successors: %bb.1, %bb.2 644 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 645 646 %0:_(<32 x s32>) = G_IMPLICIT_DEF 647 %1:_(s32) = COPY $vgpr4 648 %2:_(s32) = G_CONSTANT i32 0 649 %3:_(s1) = G_ICMP intpred(eq), %1, %2 650 G_BRCOND %3, %bb.1 651 G_BR %bb.2 652 653 bb.1: 654 successors: %bb.2 655 656 %4:_(<32 x s32>) = G_ADD %0, %0 657 G_BR %bb.2 658 659 bb.2: 660 %5:_(<32 x s32>) = G_PHI %0, %bb.0, %4, %bb.1 661 S_SETPC_B64 undef $sgpr30_sgpr31, implicit %5 662 663... 664 665--- 666name: test_phi_v64s32 667tracksRegLiveness: true 668 669body: | 670 ; CHECK-LABEL: name: test_phi_v64s32 671 ; CHECK: bb.0: 672 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 673 ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 674 ; CHECK-NEXT: {{ $}} 675 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<32 x s32>) = G_IMPLICIT_DEF 676 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr4 677 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 678 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] 679 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s32>), [[UV1:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[DEF]](<32 x s32>) 680 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<16 x s32>), [[UV3:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[DEF]](<32 x s32>) 681 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 682 ; CHECK-NEXT: G_BR %bb.2 683 ; CHECK-NEXT: {{ $}} 684 ; CHECK-NEXT: bb.1: 685 ; CHECK-NEXT: successors: %bb.2(0x80000000) 686 ; CHECK-NEXT: {{ $}} 687 ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<32 x s32>) 688 ; CHECK-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32), [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32), [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32), [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32), [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32), [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32), [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32), [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32), [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32), [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32), [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32), [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32), [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32), [[UV64:%[0-9]+]]:_(s32), [[UV65:%[0-9]+]]:_(s32), [[UV66:%[0-9]+]]:_(s32), [[UV67:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<32 x s32>) 689 ; CHECK-NEXT: [[UV68:%[0-9]+]]:_(s32), [[UV69:%[0-9]+]]:_(s32), [[UV70:%[0-9]+]]:_(s32), [[UV71:%[0-9]+]]:_(s32), [[UV72:%[0-9]+]]:_(s32), [[UV73:%[0-9]+]]:_(s32), [[UV74:%[0-9]+]]:_(s32), [[UV75:%[0-9]+]]:_(s32), [[UV76:%[0-9]+]]:_(s32), [[UV77:%[0-9]+]]:_(s32), [[UV78:%[0-9]+]]:_(s32), [[UV79:%[0-9]+]]:_(s32), [[UV80:%[0-9]+]]:_(s32), [[UV81:%[0-9]+]]:_(s32), [[UV82:%[0-9]+]]:_(s32), [[UV83:%[0-9]+]]:_(s32), [[UV84:%[0-9]+]]:_(s32), [[UV85:%[0-9]+]]:_(s32), [[UV86:%[0-9]+]]:_(s32), [[UV87:%[0-9]+]]:_(s32), [[UV88:%[0-9]+]]:_(s32), [[UV89:%[0-9]+]]:_(s32), [[UV90:%[0-9]+]]:_(s32), [[UV91:%[0-9]+]]:_(s32), [[UV92:%[0-9]+]]:_(s32), [[UV93:%[0-9]+]]:_(s32), [[UV94:%[0-9]+]]:_(s32), [[UV95:%[0-9]+]]:_(s32), [[UV96:%[0-9]+]]:_(s32), [[UV97:%[0-9]+]]:_(s32), [[UV98:%[0-9]+]]:_(s32), [[UV99:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<32 x s32>) 690 ; CHECK-NEXT: [[UV100:%[0-9]+]]:_(s32), [[UV101:%[0-9]+]]:_(s32), [[UV102:%[0-9]+]]:_(s32), [[UV103:%[0-9]+]]:_(s32), [[UV104:%[0-9]+]]:_(s32), [[UV105:%[0-9]+]]:_(s32), [[UV106:%[0-9]+]]:_(s32), [[UV107:%[0-9]+]]:_(s32), [[UV108:%[0-9]+]]:_(s32), [[UV109:%[0-9]+]]:_(s32), [[UV110:%[0-9]+]]:_(s32), [[UV111:%[0-9]+]]:_(s32), [[UV112:%[0-9]+]]:_(s32), [[UV113:%[0-9]+]]:_(s32), [[UV114:%[0-9]+]]:_(s32), [[UV115:%[0-9]+]]:_(s32), [[UV116:%[0-9]+]]:_(s32), [[UV117:%[0-9]+]]:_(s32), [[UV118:%[0-9]+]]:_(s32), [[UV119:%[0-9]+]]:_(s32), [[UV120:%[0-9]+]]:_(s32), [[UV121:%[0-9]+]]:_(s32), [[UV122:%[0-9]+]]:_(s32), [[UV123:%[0-9]+]]:_(s32), [[UV124:%[0-9]+]]:_(s32), [[UV125:%[0-9]+]]:_(s32), [[UV126:%[0-9]+]]:_(s32), [[UV127:%[0-9]+]]:_(s32), [[UV128:%[0-9]+]]:_(s32), [[UV129:%[0-9]+]]:_(s32), [[UV130:%[0-9]+]]:_(s32), [[UV131:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<32 x s32>) 691 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV4]], [[UV68]] 692 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[UV69]] 693 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV6]], [[UV70]] 694 ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV7]], [[UV71]] 695 ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UV8]], [[UV72]] 696 ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UV9]], [[UV73]] 697 ; CHECK-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[UV10]], [[UV74]] 698 ; CHECK-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UV11]], [[UV75]] 699 ; CHECK-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UV12]], [[UV76]] 700 ; CHECK-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[UV13]], [[UV77]] 701 ; CHECK-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[UV14]], [[UV78]] 702 ; CHECK-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UV15]], [[UV79]] 703 ; CHECK-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UV16]], [[UV80]] 704 ; CHECK-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[UV17]], [[UV81]] 705 ; CHECK-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[UV18]], [[UV82]] 706 ; CHECK-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UV19]], [[UV83]] 707 ; CHECK-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UV20]], [[UV84]] 708 ; CHECK-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[UV21]], [[UV85]] 709 ; CHECK-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[UV22]], [[UV86]] 710 ; CHECK-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[UV23]], [[UV87]] 711 ; CHECK-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[UV24]], [[UV88]] 712 ; CHECK-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[UV25]], [[UV89]] 713 ; CHECK-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[UV26]], [[UV90]] 714 ; CHECK-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UV27]], [[UV91]] 715 ; CHECK-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UV28]], [[UV92]] 716 ; CHECK-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[UV29]], [[UV93]] 717 ; CHECK-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[UV30]], [[UV94]] 718 ; CHECK-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[UV31]], [[UV95]] 719 ; CHECK-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[UV32]], [[UV96]] 720 ; CHECK-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UV33]], [[UV97]] 721 ; CHECK-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[UV34]], [[UV98]] 722 ; CHECK-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UV35]], [[UV99]] 723 ; CHECK-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[UV36]], [[UV100]] 724 ; CHECK-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UV37]], [[UV101]] 725 ; CHECK-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[UV38]], [[UV102]] 726 ; CHECK-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UV39]], [[UV103]] 727 ; CHECK-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[UV40]], [[UV104]] 728 ; CHECK-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[UV41]], [[UV105]] 729 ; CHECK-NEXT: [[ADD38:%[0-9]+]]:_(s32) = G_ADD [[UV42]], [[UV106]] 730 ; CHECK-NEXT: [[ADD39:%[0-9]+]]:_(s32) = G_ADD [[UV43]], [[UV107]] 731 ; CHECK-NEXT: [[ADD40:%[0-9]+]]:_(s32) = G_ADD [[UV44]], [[UV108]] 732 ; CHECK-NEXT: [[ADD41:%[0-9]+]]:_(s32) = G_ADD [[UV45]], [[UV109]] 733 ; CHECK-NEXT: [[ADD42:%[0-9]+]]:_(s32) = G_ADD [[UV46]], [[UV110]] 734 ; CHECK-NEXT: [[ADD43:%[0-9]+]]:_(s32) = G_ADD [[UV47]], [[UV111]] 735 ; CHECK-NEXT: [[ADD44:%[0-9]+]]:_(s32) = G_ADD [[UV48]], [[UV112]] 736 ; CHECK-NEXT: [[ADD45:%[0-9]+]]:_(s32) = G_ADD [[UV49]], [[UV113]] 737 ; CHECK-NEXT: [[ADD46:%[0-9]+]]:_(s32) = G_ADD [[UV50]], [[UV114]] 738 ; CHECK-NEXT: [[ADD47:%[0-9]+]]:_(s32) = G_ADD [[UV51]], [[UV115]] 739 ; CHECK-NEXT: [[ADD48:%[0-9]+]]:_(s32) = G_ADD [[UV52]], [[UV116]] 740 ; CHECK-NEXT: [[ADD49:%[0-9]+]]:_(s32) = G_ADD [[UV53]], [[UV117]] 741 ; CHECK-NEXT: [[ADD50:%[0-9]+]]:_(s32) = G_ADD [[UV54]], [[UV118]] 742 ; CHECK-NEXT: [[ADD51:%[0-9]+]]:_(s32) = G_ADD [[UV55]], [[UV119]] 743 ; CHECK-NEXT: [[ADD52:%[0-9]+]]:_(s32) = G_ADD [[UV56]], [[UV120]] 744 ; CHECK-NEXT: [[ADD53:%[0-9]+]]:_(s32) = G_ADD [[UV57]], [[UV121]] 745 ; CHECK-NEXT: [[ADD54:%[0-9]+]]:_(s32) = G_ADD [[UV58]], [[UV122]] 746 ; CHECK-NEXT: [[ADD55:%[0-9]+]]:_(s32) = G_ADD [[UV59]], [[UV123]] 747 ; CHECK-NEXT: [[ADD56:%[0-9]+]]:_(s32) = G_ADD [[UV60]], [[UV124]] 748 ; CHECK-NEXT: [[ADD57:%[0-9]+]]:_(s32) = G_ADD [[UV61]], [[UV125]] 749 ; CHECK-NEXT: [[ADD58:%[0-9]+]]:_(s32) = G_ADD [[UV62]], [[UV126]] 750 ; CHECK-NEXT: [[ADD59:%[0-9]+]]:_(s32) = G_ADD [[UV63]], [[UV127]] 751 ; CHECK-NEXT: [[ADD60:%[0-9]+]]:_(s32) = G_ADD [[UV64]], [[UV128]] 752 ; CHECK-NEXT: [[ADD61:%[0-9]+]]:_(s32) = G_ADD [[UV65]], [[UV129]] 753 ; CHECK-NEXT: [[ADD62:%[0-9]+]]:_(s32) = G_ADD [[UV66]], [[UV130]] 754 ; CHECK-NEXT: [[ADD63:%[0-9]+]]:_(s32) = G_ADD [[UV67]], [[UV131]] 755 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s32), [[ADD5]](s32), [[ADD6]](s32), [[ADD7]](s32), [[ADD8]](s32), [[ADD9]](s32), [[ADD10]](s32), [[ADD11]](s32), [[ADD12]](s32), [[ADD13]](s32), [[ADD14]](s32), [[ADD15]](s32) 756 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[ADD16]](s32), [[ADD17]](s32), [[ADD18]](s32), [[ADD19]](s32), [[ADD20]](s32), [[ADD21]](s32), [[ADD22]](s32), [[ADD23]](s32), [[ADD24]](s32), [[ADD25]](s32), [[ADD26]](s32), [[ADD27]](s32), [[ADD28]](s32), [[ADD29]](s32), [[ADD30]](s32), [[ADD31]](s32) 757 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[ADD32]](s32), [[ADD33]](s32), [[ADD34]](s32), [[ADD35]](s32), [[ADD36]](s32), [[ADD37]](s32), [[ADD38]](s32), [[ADD39]](s32), [[ADD40]](s32), [[ADD41]](s32), [[ADD42]](s32), [[ADD43]](s32), [[ADD44]](s32), [[ADD45]](s32), [[ADD46]](s32), [[ADD47]](s32) 758 ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[ADD48]](s32), [[ADD49]](s32), [[ADD50]](s32), [[ADD51]](s32), [[ADD52]](s32), [[ADD53]](s32), [[ADD54]](s32), [[ADD55]](s32), [[ADD56]](s32), [[ADD57]](s32), [[ADD58]](s32), [[ADD59]](s32), [[ADD60]](s32), [[ADD61]](s32), [[ADD62]](s32), [[ADD63]](s32) 759 ; CHECK-NEXT: G_BR %bb.2 760 ; CHECK-NEXT: {{ $}} 761 ; CHECK-NEXT: bb.2: 762 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<16 x s32>) = G_PHI [[UV]](<16 x s32>), %bb.0, [[BUILD_VECTOR]](<16 x s32>), %bb.1 763 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(<16 x s32>) = G_PHI [[UV1]](<16 x s32>), %bb.0, [[BUILD_VECTOR1]](<16 x s32>), %bb.1 764 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<16 x s32>) = G_PHI [[UV2]](<16 x s32>), %bb.0, [[BUILD_VECTOR2]](<16 x s32>), %bb.1 765 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(<16 x s32>) = G_PHI [[UV3]](<16 x s32>), %bb.0, [[BUILD_VECTOR3]](<16 x s32>), %bb.1 766 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s32>) = G_CONCAT_VECTORS [[PHI]](<16 x s32>), [[PHI1]](<16 x s32>), [[PHI2]](<16 x s32>), [[PHI3]](<16 x s32>) 767 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[CONCAT_VECTORS]](<64 x s32>) 768 bb.0: 769 successors: %bb.1, %bb.2 770 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 771 772 %0:_(<64 x s32>) = G_IMPLICIT_DEF 773 %1:_(s32) = COPY $vgpr4 774 %2:_(s32) = G_CONSTANT i32 0 775 %3:_(s1) = G_ICMP intpred(eq), %1, %2 776 G_BRCOND %3, %bb.1 777 G_BR %bb.2 778 779 bb.1: 780 successors: %bb.2 781 782 %4:_(<64 x s32>) = G_ADD %0, %0 783 G_BR %bb.2 784 785 bb.2: 786 %5:_(<64 x s32>) = G_PHI %0, %bb.0, %4, %bb.1 787 S_SETPC_B64 undef $sgpr30_sgpr31, implicit %5 788 789... 790 791--- 792name: test_phi_s64 793tracksRegLiveness: true 794 795body: | 796 ; CHECK-LABEL: name: test_phi_s64 797 ; CHECK: bb.0: 798 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 799 ; CHECK-NEXT: liveins: $vgpr0_vgpr1, $vgpr2 800 ; CHECK-NEXT: {{ $}} 801 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 802 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 803 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 804 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 805 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 806 ; CHECK-NEXT: G_BR %bb.2 807 ; CHECK-NEXT: {{ $}} 808 ; CHECK-NEXT: bb.1: 809 ; CHECK-NEXT: successors: %bb.2(0x80000000) 810 ; CHECK-NEXT: {{ $}} 811 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 812 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 813 ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]] 814 ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]] 815 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32) 816 ; CHECK-NEXT: G_BR %bb.2 817 ; CHECK-NEXT: {{ $}} 818 ; CHECK-NEXT: bb.2: 819 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY]](s64), %bb.0, [[MV]](s64), %bb.1 820 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[PHI]](s64) 821 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 822 bb.0: 823 successors: %bb.1, %bb.2 824 liveins: $vgpr0_vgpr1, $vgpr2 825 826 %0:_(s64) = COPY $vgpr0_vgpr1 827 %1:_(s32) = COPY $vgpr2 828 %2:_(s32) = G_CONSTANT i32 0 829 %3:_(s1) = G_ICMP intpred(eq), %1, %2 830 G_BRCOND %3, %bb.1 831 G_BR %bb.2 832 833 bb.1: 834 successors: %bb.2 835 836 %4:_(s64) = G_ADD %0, %0 837 G_BR %bb.2 838 839 bb.2: 840 %5:_(s64) = G_PHI %0, %bb.0, %4, %bb.1 841 $vgpr0_vgpr1 = COPY %5 842 S_SETPC_B64 undef $sgpr30_sgpr31 843 844... 845--- 846name: test_phi_v2s64 847tracksRegLiveness: true 848 849body: | 850 ; CHECK-LABEL: name: test_phi_v2s64 851 ; CHECK: bb.0: 852 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 853 ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 854 ; CHECK-NEXT: {{ $}} 855 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 856 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4 857 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 858 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 859 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 860 ; CHECK-NEXT: G_BR %bb.2 861 ; CHECK-NEXT: {{ $}} 862 ; CHECK-NEXT: bb.1: 863 ; CHECK-NEXT: successors: %bb.2(0x80000000) 864 ; CHECK-NEXT: {{ $}} 865 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) 866 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) 867 ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) 868 ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) 869 ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV4]], [[UV6]] 870 ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV5]], [[UV7]], [[UADDO1]] 871 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32) 872 ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) 873 ; CHECK-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) 874 ; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(s32), [[UADDO3:%[0-9]+]]:_(s1) = G_UADDO [[UV8]], [[UV10]] 875 ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV9]], [[UV11]], [[UADDO3]] 876 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO2]](s32), [[UADDE2]](s32) 877 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64) 878 ; CHECK-NEXT: G_BR %bb.2 879 ; CHECK-NEXT: {{ $}} 880 ; CHECK-NEXT: bb.2: 881 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<2 x s64>) = G_PHI [[COPY]](<2 x s64>), %bb.0, [[BUILD_VECTOR]](<2 x s64>), %bb.1 882 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[PHI]](<2 x s64>) 883 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 884 bb.0: 885 successors: %bb.1, %bb.2 886 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 887 888 %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 889 %1:_(s32) = COPY $vgpr4 890 %2:_(s32) = G_CONSTANT i32 0 891 %3:_(s1) = G_ICMP intpred(eq), %1, %2 892 G_BRCOND %3, %bb.1 893 G_BR %bb.2 894 895 bb.1: 896 successors: %bb.2 897 898 %4:_(<2 x s64>) = G_ADD %0, %0 899 G_BR %bb.2 900 901 bb.2: 902 %5:_(<2 x s64>) = G_PHI %0, %bb.0, %4, %bb.1 903 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5 904 S_SETPC_B64 undef $sgpr30_sgpr31 905 906... 907--- 908name: test_phi_v3s64 909tracksRegLiveness: true 910 911body: | 912 ; CHECK-LABEL: name: test_phi_v3s64 913 ; CHECK: bb.0: 914 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 915 ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8 916 ; CHECK-NEXT: {{ $}} 917 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 918 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8 919 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 920 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 921 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s64>) 922 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[UV2]](s64) 923 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 924 ; CHECK-NEXT: G_BR %bb.2 925 ; CHECK-NEXT: {{ $}} 926 ; CHECK-NEXT: bb.1: 927 ; CHECK-NEXT: successors: %bb.2(0x80000000) 928 ; CHECK-NEXT: {{ $}} 929 ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) 930 ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) 931 ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV4]], [[UV6]] 932 ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV5]], [[UV7]], [[UADDO1]] 933 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32) 934 ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) 935 ; CHECK-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) 936 ; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(s32), [[UADDO3:%[0-9]+]]:_(s1) = G_UADDO [[UV8]], [[UV10]] 937 ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV9]], [[UV11]], [[UADDO3]] 938 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO2]](s32), [[UADDE2]](s32) 939 ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) 940 ; CHECK-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) 941 ; CHECK-NEXT: [[UADDO4:%[0-9]+]]:_(s32), [[UADDO5:%[0-9]+]]:_(s1) = G_UADDO [[UV12]], [[UV14]] 942 ; CHECK-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV13]], [[UV15]], [[UADDO5]] 943 ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO4]](s32), [[UADDE4]](s32) 944 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64) 945 ; CHECK-NEXT: G_BR %bb.2 946 ; CHECK-NEXT: {{ $}} 947 ; CHECK-NEXT: bb.2: 948 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<3 x s64>) = G_PHI [[BUILD_VECTOR]](<3 x s64>), %bb.0, [[BUILD_VECTOR1]](<3 x s64>), %bb.1 949 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF 950 ; CHECK-NEXT: [[UV16:%[0-9]+]]:_(s64), [[UV17:%[0-9]+]]:_(s64), [[UV18:%[0-9]+]]:_(s64), [[UV19:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>) 951 ; CHECK-NEXT: [[UV20:%[0-9]+]]:_(s64), [[UV21:%[0-9]+]]:_(s64), [[UV22:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[PHI]](<3 x s64>) 952 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV20]](s64), [[UV21]](s64), [[UV22]](s64), [[UV19]](s64) 953 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR2]](<4 x s64>) 954 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 955 bb.0: 956 successors: %bb.1, %bb.2 957 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8 958 959 %0:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 960 %1:_(s32) = COPY $vgpr8 961 %2:_(s32) = G_CONSTANT i32 0 962 %3:_(s1) = G_ICMP intpred(eq), %1, %2 963 %4:_(<3 x s64>) = G_EXTRACT %0, 0 964 G_BRCOND %3, %bb.1 965 G_BR %bb.2 966 967 bb.1: 968 successors: %bb.2 969 970 %5:_(<3 x s64>) = G_ADD %4, %4 971 G_BR %bb.2 972 973 bb.2: 974 %6:_(<3 x s64>) = G_PHI %4, %bb.0, %5, %bb.1 975 %7:_(<4 x s64>) = G_IMPLICIT_DEF 976 %8:_(<4 x s64>) = G_INSERT %7, %6, 0 977 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %8 978 S_SETPC_B64 undef $sgpr30_sgpr31 979 980... 981--- 982name: test_phi_p3 983tracksRegLiveness: true 984 985body: | 986 ; CHECK-LABEL: name: test_phi_p3 987 ; CHECK: bb.0: 988 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 989 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 990 ; CHECK-NEXT: {{ $}} 991 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0 992 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 993 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 994 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 995 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 996 ; CHECK-NEXT: G_BR %bb.2 997 ; CHECK-NEXT: {{ $}} 998 ; CHECK-NEXT: bb.1: 999 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1000 ; CHECK-NEXT: {{ $}} 1001 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 1002 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32) 1003 ; CHECK-NEXT: G_BR %bb.2 1004 ; CHECK-NEXT: {{ $}} 1005 ; CHECK-NEXT: bb.2: 1006 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p3) = G_PHI [[COPY]](p3), %bb.0, [[PTR_ADD]](p3), %bb.1 1007 ; CHECK-NEXT: $vgpr0 = COPY [[PHI]](p3) 1008 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1009 bb.0: 1010 successors: %bb.1, %bb.2 1011 liveins: $vgpr0, $vgpr1 1012 1013 %0:_(p3) = COPY $vgpr0 1014 %1:_(s32) = COPY $vgpr1 1015 %2:_(s32) = G_CONSTANT i32 0 1016 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1017 G_BRCOND %3, %bb.1 1018 G_BR %bb.2 1019 1020 bb.1: 1021 successors: %bb.2 1022 1023 %4:_(s32) = G_CONSTANT i32 8 1024 %5:_(p3) = G_PTR_ADD %0, %4 1025 G_BR %bb.2 1026 1027 bb.2: 1028 %6:_(p3) = G_PHI %0, %bb.0, %5, %bb.1 1029 $vgpr0 = COPY %6 1030 S_SETPC_B64 undef $sgpr30_sgpr31 1031 1032... 1033--- 1034name: test_phi_p5 1035tracksRegLiveness: true 1036 1037body: | 1038 ; CHECK-LABEL: name: test_phi_p5 1039 ; CHECK: bb.0: 1040 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1041 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 1042 ; CHECK-NEXT: {{ $}} 1043 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0 1044 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 1045 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1046 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1047 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1048 ; CHECK-NEXT: G_BR %bb.2 1049 ; CHECK-NEXT: {{ $}} 1050 ; CHECK-NEXT: bb.1: 1051 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1052 ; CHECK-NEXT: {{ $}} 1053 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 1054 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C1]](s32) 1055 ; CHECK-NEXT: G_BR %bb.2 1056 ; CHECK-NEXT: {{ $}} 1057 ; CHECK-NEXT: bb.2: 1058 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p5) = G_PHI [[COPY]](p5), %bb.0, [[PTR_ADD]](p5), %bb.1 1059 ; CHECK-NEXT: $vgpr0 = COPY [[PHI]](p5) 1060 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1061 bb.0: 1062 successors: %bb.1, %bb.2 1063 liveins: $vgpr0, $vgpr1 1064 1065 %0:_(p5) = COPY $vgpr0 1066 %1:_(s32) = COPY $vgpr1 1067 %2:_(s32) = G_CONSTANT i32 0 1068 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1069 G_BRCOND %3, %bb.1 1070 G_BR %bb.2 1071 1072 bb.1: 1073 successors: %bb.2 1074 1075 %4:_(s32) = G_CONSTANT i32 8 1076 %5:_(p5) = G_PTR_ADD %0, %4 1077 G_BR %bb.2 1078 1079 bb.2: 1080 %6:_(p5) = G_PHI %0, %bb.0, %5, %bb.1 1081 $vgpr0 = COPY %6 1082 S_SETPC_B64 undef $sgpr30_sgpr31 1083 1084... 1085--- 1086name: test_phi_p0 1087tracksRegLiveness: true 1088 1089body: | 1090 ; CHECK-LABEL: name: test_phi_p0 1091 ; CHECK: bb.0: 1092 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1093 ; CHECK-NEXT: liveins: $vgpr0_vgpr1, $vgpr2 1094 ; CHECK-NEXT: {{ $}} 1095 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 1096 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 1097 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1098 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1099 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1100 ; CHECK-NEXT: G_BR %bb.2 1101 ; CHECK-NEXT: {{ $}} 1102 ; CHECK-NEXT: bb.1: 1103 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1104 ; CHECK-NEXT: {{ $}} 1105 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 1106 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64) 1107 ; CHECK-NEXT: G_BR %bb.2 1108 ; CHECK-NEXT: {{ $}} 1109 ; CHECK-NEXT: bb.2: 1110 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY]](p0), %bb.0, [[PTR_ADD]](p0), %bb.1 1111 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[PHI]](p0) 1112 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1113 bb.0: 1114 successors: %bb.1, %bb.2 1115 liveins: $vgpr0_vgpr1, $vgpr2 1116 1117 %0:_(p0) = COPY $vgpr0_vgpr1 1118 %1:_(s32) = COPY $vgpr2 1119 %2:_(s32) = G_CONSTANT i32 0 1120 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1121 G_BRCOND %3, %bb.1 1122 G_BR %bb.2 1123 1124 bb.1: 1125 successors: %bb.2 1126 1127 %4:_(s64) = G_CONSTANT i64 8 1128 %5:_(p0) = G_PTR_ADD %0, %4 1129 G_BR %bb.2 1130 1131 bb.2: 1132 %6:_(p0) = G_PHI %0, %bb.0, %5, %bb.1 1133 $vgpr0_vgpr1 = COPY %6 1134 S_SETPC_B64 undef $sgpr30_sgpr31 1135 1136... 1137--- 1138name: test_phi_p1 1139tracksRegLiveness: true 1140 1141body: | 1142 ; CHECK-LABEL: name: test_phi_p1 1143 ; CHECK: bb.0: 1144 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1145 ; CHECK-NEXT: liveins: $vgpr0_vgpr1, $vgpr2 1146 ; CHECK-NEXT: {{ $}} 1147 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 1148 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 1149 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1150 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1151 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1152 ; CHECK-NEXT: G_BR %bb.2 1153 ; CHECK-NEXT: {{ $}} 1154 ; CHECK-NEXT: bb.1: 1155 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1156 ; CHECK-NEXT: {{ $}} 1157 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 1158 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64) 1159 ; CHECK-NEXT: G_BR %bb.2 1160 ; CHECK-NEXT: {{ $}} 1161 ; CHECK-NEXT: bb.2: 1162 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p1) = G_PHI [[COPY]](p1), %bb.0, [[PTR_ADD]](p1), %bb.1 1163 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[PHI]](p1) 1164 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1165 bb.0: 1166 successors: %bb.1, %bb.2 1167 liveins: $vgpr0_vgpr1, $vgpr2 1168 1169 %0:_(p1) = COPY $vgpr0_vgpr1 1170 %1:_(s32) = COPY $vgpr2 1171 %2:_(s32) = G_CONSTANT i32 0 1172 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1173 G_BRCOND %3, %bb.1 1174 G_BR %bb.2 1175 1176 bb.1: 1177 successors: %bb.2 1178 1179 %4:_(s64) = G_CONSTANT i64 8 1180 %5:_(p1) = G_PTR_ADD %0, %4 1181 G_BR %bb.2 1182 1183 bb.2: 1184 %6:_(p1) = G_PHI %0, %bb.0, %5, %bb.1 1185 $vgpr0_vgpr1 = COPY %6 1186 S_SETPC_B64 undef $sgpr30_sgpr31 1187 1188... 1189--- 1190name: test_phi_p4 1191tracksRegLiveness: true 1192 1193body: | 1194 ; CHECK-LABEL: name: test_phi_p4 1195 ; CHECK: bb.0: 1196 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1197 ; CHECK-NEXT: liveins: $vgpr0_vgpr1, $vgpr2 1198 ; CHECK-NEXT: {{ $}} 1199 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 1200 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 1201 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1202 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1203 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1204 ; CHECK-NEXT: G_BR %bb.2 1205 ; CHECK-NEXT: {{ $}} 1206 ; CHECK-NEXT: bb.1: 1207 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1208 ; CHECK-NEXT: {{ $}} 1209 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 1210 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64) 1211 ; CHECK-NEXT: G_BR %bb.2 1212 ; CHECK-NEXT: {{ $}} 1213 ; CHECK-NEXT: bb.2: 1214 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p4) = G_PHI [[COPY]](p4), %bb.0, [[PTR_ADD]](p4), %bb.1 1215 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[PHI]](p4) 1216 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1217 bb.0: 1218 successors: %bb.1, %bb.2 1219 liveins: $vgpr0_vgpr1, $vgpr2 1220 1221 %0:_(p4) = COPY $vgpr0_vgpr1 1222 %1:_(s32) = COPY $vgpr2 1223 %2:_(s32) = G_CONSTANT i32 0 1224 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1225 G_BRCOND %3, %bb.1 1226 G_BR %bb.2 1227 1228 bb.1: 1229 successors: %bb.2 1230 1231 %4:_(s64) = G_CONSTANT i64 8 1232 %5:_(p4) = G_PTR_ADD %0, %4 1233 G_BR %bb.2 1234 1235 bb.2: 1236 %6:_(p4) = G_PHI %0, %bb.0, %5, %bb.1 1237 $vgpr0_vgpr1 = COPY %6 1238 S_SETPC_B64 undef $sgpr30_sgpr31 1239 1240... 1241--- 1242name: test_phi_p9999 1243tracksRegLiveness: true 1244 1245body: | 1246 ; CHECK-LABEL: name: test_phi_p9999 1247 ; CHECK: bb.0: 1248 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1249 ; CHECK-NEXT: liveins: $vgpr0_vgpr1, $vgpr2 1250 ; CHECK-NEXT: {{ $}} 1251 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p9999) = COPY $vgpr0_vgpr1 1252 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 1253 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1254 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1255 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1256 ; CHECK-NEXT: G_BR %bb.2 1257 ; CHECK-NEXT: {{ $}} 1258 ; CHECK-NEXT: bb.1: 1259 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1260 ; CHECK-NEXT: {{ $}} 1261 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p9999) = G_IMPLICIT_DEF 1262 ; CHECK-NEXT: G_BR %bb.2 1263 ; CHECK-NEXT: {{ $}} 1264 ; CHECK-NEXT: bb.2: 1265 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p9999) = G_PHI [[COPY]](p9999), %bb.0, [[DEF]](p9999), %bb.1 1266 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[PHI]](p9999) 1267 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1268 bb.0: 1269 successors: %bb.1, %bb.2 1270 liveins: $vgpr0_vgpr1, $vgpr2 1271 1272 %0:_(p9999) = COPY $vgpr0_vgpr1 1273 %1:_(s32) = COPY $vgpr2 1274 %2:_(s32) = G_CONSTANT i32 0 1275 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1276 G_BRCOND %3, %bb.1 1277 G_BR %bb.2 1278 1279 bb.1: 1280 successors: %bb.2 1281 1282 %4:_(p9999) = G_IMPLICIT_DEF 1283 G_BR %bb.2 1284 1285 bb.2: 1286 %5:_(p9999) = G_PHI %0, %bb.0, %4, %bb.1 1287 $vgpr0_vgpr1 = COPY %5 1288 S_SETPC_B64 undef $sgpr30_sgpr31 1289 1290... 1291--- 1292name: test_phi_s1 1293tracksRegLiveness: true 1294 1295body: | 1296 ; CHECK-LABEL: name: test_phi_s1 1297 ; CHECK: bb.0: 1298 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1299 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 1300 ; CHECK-NEXT: {{ $}} 1301 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 1302 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 1303 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1304 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1305 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s32) 1306 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1307 ; CHECK-NEXT: G_BR %bb.2 1308 ; CHECK-NEXT: {{ $}} 1309 ; CHECK-NEXT: bb.1: 1310 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1311 ; CHECK-NEXT: {{ $}} 1312 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF 1313 ; CHECK-NEXT: G_BR %bb.2 1314 ; CHECK-NEXT: {{ $}} 1315 ; CHECK-NEXT: bb.2: 1316 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[TRUNC]](s1), %bb.0, [[DEF]](s1), %bb.1 1317 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[PHI]](s1) 1318 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXT]](s32) 1319 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1320 bb.0: 1321 successors: %bb.1, %bb.2 1322 liveins: $vgpr0, $vgpr1 1323 1324 %0:_(s32) = COPY $vgpr0 1325 %1:_(s32) = COPY $vgpr1 1326 %2:_(s32) = G_CONSTANT i32 0 1327 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1328 %4:_(s1) = G_TRUNC %1 1329 G_BRCOND %3, %bb.1 1330 G_BR %bb.2 1331 1332 bb.1: 1333 successors: %bb.2 1334 1335 %5:_(s1) = G_IMPLICIT_DEF 1336 G_BR %bb.2 1337 1338 bb.2: 1339 %6:_(s1) = G_PHI %4, %bb.0, %5, %bb.1 1340 %7:_(s32) = G_ZEXT %6 1341 $vgpr0 = COPY %7 1342 S_SETPC_B64 undef $sgpr30_sgpr31 1343 1344... 1345--- 1346name: test_phi_s7 1347tracksRegLiveness: true 1348 1349body: | 1350 ; CHECK-LABEL: name: test_phi_s7 1351 ; CHECK: bb.0: 1352 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1353 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 1354 ; CHECK-NEXT: {{ $}} 1355 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 1356 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 1357 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1358 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1359 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 1360 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1361 ; CHECK-NEXT: G_BR %bb.2 1362 ; CHECK-NEXT: {{ $}} 1363 ; CHECK-NEXT: bb.1: 1364 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1365 ; CHECK-NEXT: {{ $}} 1366 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF 1367 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32) 1368 ; CHECK-NEXT: G_BR %bb.2 1369 ; CHECK-NEXT: {{ $}} 1370 ; CHECK-NEXT: bb.2: 1371 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, [[TRUNC1]](s16), %bb.1 1372 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16) 1373 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 1374 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]] 1375 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32) 1376 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1377 bb.0: 1378 successors: %bb.1, %bb.2 1379 liveins: $vgpr0, $vgpr1 1380 1381 %0:_(s32) = COPY $vgpr0 1382 %1:_(s32) = COPY $vgpr1 1383 %2:_(s32) = G_CONSTANT i32 0 1384 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1385 %4:_(s7) = G_TRUNC %1 1386 G_BRCOND %3, %bb.1 1387 G_BR %bb.2 1388 1389 bb.1: 1390 successors: %bb.2 1391 1392 %5:_(s7) = G_IMPLICIT_DEF 1393 G_BR %bb.2 1394 1395 bb.2: 1396 %6:_(s7) = G_PHI %4, %bb.0, %5, %bb.1 1397 %7:_(s32) = G_ZEXT %6 1398 $vgpr0 = COPY %7 1399 S_SETPC_B64 undef $sgpr30_sgpr31 1400 1401... 1402--- 1403name: test_phi_s8 1404tracksRegLiveness: true 1405 1406body: | 1407 ; CHECK-LABEL: name: test_phi_s8 1408 ; CHECK: bb.0: 1409 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1410 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 1411 ; CHECK-NEXT: {{ $}} 1412 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 1413 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 1414 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1415 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1416 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 1417 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1418 ; CHECK-NEXT: G_BR %bb.2 1419 ; CHECK-NEXT: {{ $}} 1420 ; CHECK-NEXT: bb.1: 1421 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1422 ; CHECK-NEXT: {{ $}} 1423 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF 1424 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32) 1425 ; CHECK-NEXT: G_BR %bb.2 1426 ; CHECK-NEXT: {{ $}} 1427 ; CHECK-NEXT: bb.2: 1428 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, [[TRUNC1]](s16), %bb.1 1429 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16) 1430 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 1431 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]] 1432 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32) 1433 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1434 bb.0: 1435 successors: %bb.1, %bb.2 1436 liveins: $vgpr0, $vgpr1 1437 1438 %0:_(s32) = COPY $vgpr0 1439 %1:_(s32) = COPY $vgpr1 1440 %2:_(s32) = G_CONSTANT i32 0 1441 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1442 %4:_(s8) = G_TRUNC %1 1443 G_BRCOND %3, %bb.1 1444 G_BR %bb.2 1445 1446 bb.1: 1447 successors: %bb.2 1448 1449 %5:_(s8) = G_IMPLICIT_DEF 1450 G_BR %bb.2 1451 1452 bb.2: 1453 %6:_(s8) = G_PHI %4, %bb.0, %5, %bb.1 1454 %7:_(s32) = G_ZEXT %6 1455 $vgpr0 = COPY %7 1456 S_SETPC_B64 undef $sgpr30_sgpr31 1457 1458... 1459--- 1460name: test_phi_s16 1461tracksRegLiveness: true 1462 1463body: | 1464 ; CHECK-LABEL: name: test_phi_s16 1465 ; CHECK: bb.0: 1466 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1467 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 1468 ; CHECK-NEXT: {{ $}} 1469 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 1470 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 1471 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1472 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1473 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 1474 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1475 ; CHECK-NEXT: G_BR %bb.2 1476 ; CHECK-NEXT: {{ $}} 1477 ; CHECK-NEXT: bb.1: 1478 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1479 ; CHECK-NEXT: {{ $}} 1480 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF 1481 ; CHECK-NEXT: G_BR %bb.2 1482 ; CHECK-NEXT: {{ $}} 1483 ; CHECK-NEXT: bb.2: 1484 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, [[DEF]](s16), %bb.1 1485 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[PHI]](s16) 1486 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXT]](s32) 1487 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1488 bb.0: 1489 successors: %bb.1, %bb.2 1490 liveins: $vgpr0, $vgpr1 1491 1492 %0:_(s32) = COPY $vgpr0 1493 %1:_(s32) = COPY $vgpr1 1494 %2:_(s32) = G_CONSTANT i32 0 1495 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1496 %4:_(s16) = G_TRUNC %1 1497 G_BRCOND %3, %bb.1 1498 G_BR %bb.2 1499 1500 bb.1: 1501 successors: %bb.2 1502 1503 %5:_(s16) = G_IMPLICIT_DEF 1504 G_BR %bb.2 1505 1506 bb.2: 1507 %6:_(s16) = G_PHI %4, %bb.0, %5, %bb.1 1508 %7:_(s32) = G_ZEXT %6 1509 $vgpr0 = COPY %7 1510 S_SETPC_B64 undef $sgpr30_sgpr31 1511 1512... 1513--- 1514name: test_phi_s128 1515tracksRegLiveness: true 1516 1517body: | 1518 ; CHECK-LABEL: name: test_phi_s128 1519 ; CHECK: bb.0: 1520 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1521 ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 1522 ; CHECK-NEXT: {{ $}} 1523 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 1524 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4 1525 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1526 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1527 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1528 ; CHECK-NEXT: G_BR %bb.2 1529 ; CHECK-NEXT: {{ $}} 1530 ; CHECK-NEXT: bb.1: 1531 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1532 ; CHECK-NEXT: {{ $}} 1533 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128) 1534 ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128) 1535 ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV4]] 1536 ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV5]], [[UADDO1]] 1537 ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV6]], [[UADDE1]] 1538 ; CHECK-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV3]], [[UV7]], [[UADDE3]] 1539 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32), [[UADDE2]](s32), [[UADDE4]](s32) 1540 ; CHECK-NEXT: G_BR %bb.2 1541 ; CHECK-NEXT: {{ $}} 1542 ; CHECK-NEXT: bb.2: 1543 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s128) = G_PHI [[COPY]](s128), %bb.0, [[MV]](s128), %bb.1 1544 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[PHI]](s128) 1545 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1546 bb.0: 1547 successors: %bb.1, %bb.2 1548 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 1549 1550 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 1551 %1:_(s32) = COPY $vgpr4 1552 %2:_(s32) = G_CONSTANT i32 0 1553 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1554 G_BRCOND %3, %bb.1 1555 G_BR %bb.2 1556 1557 bb.1: 1558 successors: %bb.2 1559 1560 %4:_(s128) = G_ADD %0, %0 1561 G_BR %bb.2 1562 1563 bb.2: 1564 %5:_(s128) = G_PHI %0, %bb.0, %4, %bb.1 1565 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5 1566 S_SETPC_B64 undef $sgpr30_sgpr31 1567 1568... 1569--- 1570name: test_phi_s256 1571tracksRegLiveness: true 1572 1573body: | 1574 ; CHECK-LABEL: name: test_phi_s256 1575 ; CHECK: bb.0: 1576 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1577 ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8 1578 ; CHECK-NEXT: {{ $}} 1579 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 1580 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8 1581 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1582 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] 1583 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.1 1584 ; CHECK-NEXT: G_BR %bb.2 1585 ; CHECK-NEXT: {{ $}} 1586 ; CHECK-NEXT: bb.1: 1587 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1588 ; CHECK-NEXT: {{ $}} 1589 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s256) 1590 ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s256) 1591 ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV8]] 1592 ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV9]], [[UADDO1]] 1593 ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV10]], [[UADDE1]] 1594 ; CHECK-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV3]], [[UV11]], [[UADDE3]] 1595 ; CHECK-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UV4]], [[UV12]], [[UADDE5]] 1596 ; CHECK-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UV5]], [[UV13]], [[UADDE7]] 1597 ; CHECK-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UV6]], [[UV14]], [[UADDE9]] 1598 ; CHECK-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UV7]], [[UV15]], [[UADDE11]] 1599 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32), [[UADDE2]](s32), [[UADDE4]](s32), [[UADDE6]](s32), [[UADDE8]](s32), [[UADDE10]](s32), [[UADDE12]](s32) 1600 ; CHECK-NEXT: G_BR %bb.2 1601 ; CHECK-NEXT: {{ $}} 1602 ; CHECK-NEXT: bb.2: 1603 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s256) = G_PHI [[COPY]](s256), %bb.0, [[MV]](s256), %bb.1 1604 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[PHI]](s256) 1605 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1606 bb.0: 1607 successors: %bb.1, %bb.2 1608 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8 1609 1610 %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 1611 %1:_(s32) = COPY $vgpr8 1612 %2:_(s32) = G_CONSTANT i32 0 1613 %3:_(s1) = G_ICMP intpred(eq), %1, %2 1614 G_BRCOND %3, %bb.1 1615 G_BR %bb.2 1616 1617 bb.1: 1618 successors: %bb.2 1619 1620 %4:_(s256) = G_ADD %0, %0 1621 G_BR %bb.2 1622 1623 bb.2: 1624 %5:_(s256) = G_PHI %0, %bb.0, %4, %bb.1 1625 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %5 1626 S_SETPC_B64 undef $sgpr30_sgpr31 1627 1628... 1629--- 1630name: test_phi_v2s1 1631tracksRegLiveness: true 1632 1633body: | 1634 ; CHECK-LABEL: name: test_phi_v2s1 1635 ; CHECK: bb.0: 1636 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 1637 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 1638 ; CHECK-NEXT: {{ $}} 1639 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 1640 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 1641 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2 1642 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr1 1643 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1644 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) 1645 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 1646 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32) 1647 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) 1648 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32) 1649 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 1650 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]] 1651 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]] 1652 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[AND1]] 1653 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LSHR]](s32), [[LSHR1]] 1654 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]] 1655 ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.1 1656 ; CHECK-NEXT: G_BR %bb.2 1657 ; CHECK-NEXT: {{ $}} 1658 ; CHECK-NEXT: bb.1: 1659 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1660 ; CHECK-NEXT: {{ $}} 1661 ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) 1662 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 1663 ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C3]](s32) 1664 ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY2]](<2 x s16>) 1665 ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C3]](s32) 1666 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 1667 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]] 1668 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]] 1669 ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND2]](s32), [[AND3]] 1670 ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LSHR2]](s32), [[LSHR3]] 1671 ; CHECK-NEXT: G_BR %bb.2 1672 ; CHECK-NEXT: {{ $}} 1673 ; CHECK-NEXT: bb.2: 1674 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP3]](s1), %bb.1 1675 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s1) = G_PHI [[ICMP1]](s1), %bb.0, [[ICMP4]](s1), %bb.1 1676 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s1) 1677 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s1) 1678 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 1679 ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C5]] 1680 ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C5]] 1681 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[AND5]](s32) 1682 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) 1683 ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 1684 bb.0: 1685 successors: %bb.1, %bb.2 1686 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 1687 1688 %0:_(<2 x s16>) = COPY $vgpr0 1689 %1:_(<2 x s16>) = COPY $vgpr1 1690 %2:_(<2 x s16>) = COPY $vgpr2 1691 %3:_(s32) = COPY $vgpr1 1692 %4:_(s32) = G_CONSTANT i32 0 1693 %5:_(<2 x s1>) = G_ICMP intpred(eq), %0, %1 1694 %6:_(s1) = G_ICMP intpred(eq), %3, %4 1695 G_BRCOND %6, %bb.1 1696 G_BR %bb.2 1697 1698 bb.1: 1699 successors: %bb.2 1700 1701 %7:_(<2 x s1>) = G_ICMP intpred(ne), %0, %2 1702 G_BR %bb.2 1703 1704 bb.2: 1705 %8:_(<2 x s1>) = G_PHI %5, %bb.0, %7, %bb.1 1706 %9:_(<2 x s32>) = G_ZEXT %8 1707 $vgpr0_vgpr1 = COPY %9 1708 S_SETPC_B64 undef $sgpr30_sgpr31 1709... 1710