1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -O0 -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=irtranslator -o - %s | FileCheck %s 3 4; The CSEMIRBuilder was mishandling the result operand when constant 5; folding a vector operation, resulting in a missing def for the 6; stored value. 7define amdgpu_kernel void @constant_fold_vector_add() { 8 ; CHECK-LABEL: name: constant_fold_vector_add 9 ; CHECK: bb.1.entry: 10 ; CHECK-NEXT: liveins: $sgpr8_sgpr9 11 ; CHECK-NEXT: {{ $}} 12 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9 13 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 14 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64) 15 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(p1) = G_CONSTANT i64 0 16 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 17 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64), [[C2]](s64), [[C2]](s64) 18 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<4 x s64>), [[C1]](p1) :: (store (<4 x s64>) into `ptr addrspace(1) null`, addrspace 1) 19 ; CHECK-NEXT: S_ENDPGM 0 20entry: 21 %add = add <4 x i64> zeroinitializer, zeroinitializer 22 store <4 x i64> %add, ptr addrspace(1) null, align 32 23 ret void 24} 25 26!llvm.module.flags = !{!0} 27!0 = !{i32 1, !"amdhsa_code_object_version", i32 500} 28