1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=irtranslator %s -o - | FileCheck %s 3 4define amdgpu_vs void @test_f32_inreg(float inreg %arg0) { 5 ; CHECK-LABEL: name: test_f32_inreg 6 ; CHECK: bb.1 (%ir-block.0): 7 ; CHECK-NEXT: liveins: $sgpr2 8 ; CHECK-NEXT: {{ $}} 9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 10 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF 11 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0 12 ; CHECK-NEXT: S_ENDPGM 0 13 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 14 ret void 15} 16 17define amdgpu_vs void @test_f32(float %arg0) { 18 ; CHECK-LABEL: name: test_f32 19 ; CHECK: bb.1 (%ir-block.0): 20 ; CHECK-NEXT: liveins: $vgpr0 21 ; CHECK-NEXT: {{ $}} 22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 23 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF 24 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0 25 ; CHECK-NEXT: S_ENDPGM 0 26 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 27 ret void 28} 29 30define amdgpu_vs void @test_ptr2_inreg(ptr addrspace(4) inreg %arg0) { 31 ; CHECK-LABEL: name: test_ptr2_inreg 32 ; CHECK: bb.1 (%ir-block.0): 33 ; CHECK-NEXT: liveins: $sgpr2, $sgpr3 34 ; CHECK-NEXT: {{ $}} 35 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 36 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 37 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 38 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (volatile invariant load (s32) from %ir.arg0, addrspace 4) 39 ; CHECK-NEXT: S_ENDPGM 0 40 %tmp0 = load volatile i32, ptr addrspace(4) %arg0 41 ret void 42} 43 44define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, ptr addrspace(4) inreg %arg1) { 45 ; CHECK-LABEL: name: test_sgpr_alignment0 46 ; CHECK: bb.1 (%ir-block.0): 47 ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4 48 ; CHECK-NEXT: {{ $}} 49 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 50 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 51 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 52 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) 53 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF 54 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (volatile invariant load (s32) from %ir.arg1, addrspace 4) 55 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0 56 ; CHECK-NEXT: S_ENDPGM 0 57 %tmp0 = load volatile i32, ptr addrspace(4) %arg1 58 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 59 ret void 60} 61 62define amdgpu_vs void @test_order(float inreg %arg0, float inreg %arg1, float %arg2, float %arg3) { 63 ; CHECK-LABEL: name: test_order 64 ; CHECK: bb.1 (%ir-block.0): 65 ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1 66 ; CHECK-NEXT: {{ $}} 67 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 68 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 69 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr0 70 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr1 71 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY2]](s32), [[COPY]](s32), [[COPY3]](s32), [[COPY1]](s32), 0, 0 72 ; CHECK-NEXT: S_ENDPGM 0 73 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg2, float %arg0, float %arg3, float %arg1, i1 false, i1 false) #0 74 ret void 75} 76 77define amdgpu_vs <{ i32, i32 }> @ret_struct(i32 inreg %arg0, i32 inreg %arg1) { 78 ; CHECK-LABEL: name: ret_struct 79 ; CHECK: bb.1.main_body: 80 ; CHECK-NEXT: liveins: $sgpr2, $sgpr3 81 ; CHECK-NEXT: {{ $}} 82 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 83 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 84 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF 85 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY]](s32) 86 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) 87 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32) 88 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) 89 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 90main_body: 91 %tmp0 = insertvalue <{ i32, i32 }> undef, i32 %arg0, 0 92 %tmp1 = insertvalue <{ i32, i32 }> %tmp0, i32 %arg1, 1 93 ret <{ i32, i32 }> %tmp1 94} 95 96define amdgpu_vs i32 @non_void_ret() { 97 ; CHECK-LABEL: name: non_void_ret 98 ; CHECK: bb.1 (%ir-block.0): 99 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 100 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[C]](s32) 101 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) 102 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 103 ret i32 0 104} 105 106declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 107 108attributes #0 = { nounwind } 109