xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=SI %s
3# RUN: FileCheck -check-prefix=ERR  %s < %t
4# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
5# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
6# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
7
8# ERR-NOT: remark:
9# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_SMULH %0:sgpr, %1:sgpr (in function: smulh_s32_ss)
10# ERR-NOT: remark:
11
12---
13name: smulh_s32_ss
14legalized: true
15regBankSelected: true
16
17body: |
18  bb.0:
19    liveins: $sgpr0, $sgpr1
20
21    ; SI-LABEL: name: smulh_s32_ss
22    ; SI: liveins: $sgpr0, $sgpr1
23    ; SI-NEXT: {{  $}}
24    ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
25    ; SI-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
26    ; SI-NEXT: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
27    ; SI-NEXT: S_ENDPGM 0, implicit [[SMULH]](s32)
28    ; GFX9-LABEL: name: smulh_s32_ss
29    ; GFX9: liveins: $sgpr0, $sgpr1
30    ; GFX9-NEXT: {{  $}}
31    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
32    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
33    ; GFX9-NEXT: [[S_MUL_HI_I32_:%[0-9]+]]:sreg_32 = S_MUL_HI_I32 [[COPY]], [[COPY1]]
34    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MUL_HI_I32_]]
35    %0:sgpr(s32) = COPY $sgpr0
36    %1:sgpr(s32) = COPY $sgpr1
37    %2:sgpr(s32) = G_SMULH %0, %1
38    S_ENDPGM 0, implicit %2
39...
40
41---
42name: smulh_s32_sv
43legalized: true
44regBankSelected: true
45
46body: |
47  bb.0:
48    liveins: $sgpr0, $vgpr0
49
50    ; SI-LABEL: name: smulh_s32_sv
51    ; SI: liveins: $sgpr0, $vgpr0
52    ; SI-NEXT: {{  $}}
53    ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
54    ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
55    ; SI-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
56    ; SI-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
57    ; GFX9-LABEL: name: smulh_s32_sv
58    ; GFX9: liveins: $sgpr0, $vgpr0
59    ; GFX9-NEXT: {{  $}}
60    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
61    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
62    ; GFX9-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
63    ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
64    %0:sgpr(s32) = COPY $sgpr0
65    %1:vgpr(s32) = COPY $vgpr0
66    %2:vgpr(s32) = G_SMULH %0, %1
67    S_ENDPGM 0, implicit %2
68...
69
70---
71name: smulh_s32_vs
72legalized: true
73regBankSelected: true
74
75body: |
76  bb.0:
77    liveins: $sgpr0, $vgpr0
78
79    ; SI-LABEL: name: smulh_s32_vs
80    ; SI: liveins: $sgpr0, $vgpr0
81    ; SI-NEXT: {{  $}}
82    ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
83    ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
84    ; SI-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
85    ; SI-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
86    ; GFX9-LABEL: name: smulh_s32_vs
87    ; GFX9: liveins: $sgpr0, $vgpr0
88    ; GFX9-NEXT: {{  $}}
89    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
90    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
91    ; GFX9-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
92    ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
93    %0:vgpr(s32) = COPY $vgpr0
94    %1:sgpr(s32) = COPY $sgpr0
95    %2:vgpr(s32) = G_SMULH %0, %1
96    S_ENDPGM 0, implicit %2
97...
98
99---
100name: smulh_s32_vv
101legalized: true
102regBankSelected: true
103
104body: |
105  bb.0:
106    liveins: $vgpr0, $vgpr1
107
108    ; SI-LABEL: name: smulh_s32_vv
109    ; SI: liveins: $vgpr0, $vgpr1
110    ; SI-NEXT: {{  $}}
111    ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
112    ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
113    ; SI-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
114    ; SI-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
115    ; GFX9-LABEL: name: smulh_s32_vv
116    ; GFX9: liveins: $vgpr0, $vgpr1
117    ; GFX9-NEXT: {{  $}}
118    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
119    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
120    ; GFX9-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
121    ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
122    %0:vgpr(s32) = COPY $vgpr0
123    %1:vgpr(s32) = COPY $vgpr1
124    %2:vgpr(s32) = G_SMULH %0, %1
125    S_ENDPGM 0, implicit %2
126...
127