1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s 3 4# The only instruction selection cases for G_SBFX/G_UBFX are the 64-bit 5# vector versions. All other versions, scalar and 32-bit vector, are 6# expanded during register bank selection. 7 8--- 9name: sbfx_s32_vii 10legalized: true 11regBankSelected: true 12tracksRegLiveness: true 13body: | 14 bb.0: 15 liveins: $vgpr0 16 ; CHECK-LABEL: name: sbfx_s32_vii 17 ; CHECK: liveins: $vgpr0 18 ; CHECK-NEXT: {{ $}} 19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 20 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec 21 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 10, implicit $exec 22 ; CHECK-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], implicit $exec 23 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BFE_I32_e64_]] 24 %0:vgpr(s32) = COPY $vgpr0 25 %1:vgpr(s32) = G_CONSTANT i32 2 26 %2:vgpr(s32) = G_CONSTANT i32 10 27 %3:vgpr(s32) = G_SBFX %0, %1(s32), %2 28 S_ENDPGM 0, implicit %3 29... 30 31--- 32name: sbfx_s32_vvv 33legalized: true 34regBankSelected: true 35tracksRegLiveness: true 36body: | 37 bb.0: 38 liveins: $vgpr0, $vgpr1, $vgpr2 39 ; CHECK-LABEL: name: sbfx_s32_vvv 40 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 41 ; CHECK-NEXT: {{ $}} 42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 43 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 44 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 45 ; CHECK-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec 46 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BFE_I32_e64_]] 47 %0:vgpr(s32) = COPY $vgpr0 48 %1:vgpr(s32) = COPY $vgpr1 49 %2:vgpr(s32) = COPY $vgpr2 50 %3:vgpr(s32) = G_SBFX %0, %1(s32), %2 51 S_ENDPGM 0, implicit %3 52... 53