xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
3
4---
5name: mul_s32_ss
6legalized: true
7regBankSelected: true
8
9body: |
10  bb.0:
11    liveins: $sgpr0, $sgpr1
12    ; GCN-LABEL: name: mul_s32_ss
13    ; GCN: liveins: $sgpr0, $sgpr1
14    ; GCN-NEXT: {{  $}}
15    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
16    ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
17    ; GCN-NEXT: [[S_MUL_I32_:%[0-9]+]]:sreg_32 = S_MUL_I32 [[COPY]], [[COPY1]]
18    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_MUL_I32_]]
19    %0:sgpr(s32) = COPY $sgpr0
20    %1:sgpr(s32) = COPY $sgpr1
21    %2:sgpr(s32) = G_MUL %0, %1
22    S_ENDPGM 0, implicit %2
23...
24
25---
26name: mul_s32_sv
27legalized: true
28regBankSelected: true
29
30body: |
31  bb.0:
32    liveins: $sgpr0, $vgpr0
33    ; GCN-LABEL: name: mul_s32_sv
34    ; GCN: liveins: $sgpr0, $vgpr0
35    ; GCN-NEXT: {{  $}}
36    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
37    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
38    ; GCN-NEXT: [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 [[COPY]], [[COPY1]], implicit $exec
39    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MUL_LO_U32_e64_]]
40    %0:sgpr(s32) = COPY $sgpr0
41    %1:vgpr(s32) = COPY $vgpr0
42    %2:vgpr(s32) = G_MUL %0, %1
43    S_ENDPGM 0, implicit %2
44...
45
46---
47name: mul_s32_vs
48legalized: true
49regBankSelected: true
50
51body: |
52  bb.0:
53    liveins: $sgpr0, $vgpr0
54    ; GCN-LABEL: name: mul_s32_vs
55    ; GCN: liveins: $sgpr0, $vgpr0
56    ; GCN-NEXT: {{  $}}
57    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
58    ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
59    ; GCN-NEXT: [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 [[COPY]], [[COPY1]], implicit $exec
60    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MUL_LO_U32_e64_]]
61    %0:vgpr(s32) = COPY $vgpr0
62    %1:sgpr(s32) = COPY $sgpr0
63    %2:vgpr(s32) = G_MUL %0, %1
64    S_ENDPGM 0, implicit %2
65...
66
67---
68name: mul_s32_vv
69legalized: true
70regBankSelected: true
71
72body: |
73  bb.0:
74    liveins: $vgpr0, $vgpr1
75    ; GCN-LABEL: name: mul_s32_vv
76    ; GCN: liveins: $vgpr0, $vgpr1
77    ; GCN-NEXT: {{  $}}
78    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
79    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
80    ; GCN-NEXT: [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 [[COPY]], [[COPY1]], implicit $exec
81    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MUL_LO_U32_e64_]]
82    %0:vgpr(s32) = COPY $vgpr0
83    %1:vgpr(s32) = COPY $vgpr1
84    %2:vgpr(s32) = G_MUL %0, %1
85    S_ENDPGM 0, implicit %2
86...
87