1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=SI %s 3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=VI %s 4# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s 5# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s 6# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s 7 8--- 9name: fneg_s32_ss 10legalized: true 11regBankSelected: true 12tracksRegLiveness: true 13 14body: | 15 bb.0: 16 liveins: $sgpr0 17 ; SI-LABEL: name: fneg_s32_ss 18 ; SI: liveins: $sgpr0 19 ; SI-NEXT: {{ $}} 20 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 21 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 22 ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 23 ; SI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 24 ; 25 ; VI-LABEL: name: fneg_s32_ss 26 ; VI: liveins: $sgpr0 27 ; VI-NEXT: {{ $}} 28 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 29 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 30 ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 31 ; VI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 32 ; 33 ; GFX9-LABEL: name: fneg_s32_ss 34 ; GFX9: liveins: $sgpr0 35 ; GFX9-NEXT: {{ $}} 36 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 37 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 38 ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 39 ; GFX9-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 40 ; 41 ; GFX10-LABEL: name: fneg_s32_ss 42 ; GFX10: liveins: $sgpr0 43 ; GFX10-NEXT: {{ $}} 44 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 45 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 46 ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 47 ; GFX10-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 48 %0:sgpr(s32) = COPY $sgpr0 49 %1:sgpr(s32) = G_FNEG %0 50 $sgpr0 = COPY %1 51... 52 53--- 54name: fneg_s32_vv 55legalized: true 56regBankSelected: true 57tracksRegLiveness: true 58 59body: | 60 bb.0: 61 liveins: $vgpr0 62 ; SI-LABEL: name: fneg_s32_vv 63 ; SI: liveins: $vgpr0 64 ; SI-NEXT: {{ $}} 65 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 66 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 67 ; SI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 68 ; SI-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 69 ; 70 ; VI-LABEL: name: fneg_s32_vv 71 ; VI: liveins: $vgpr0 72 ; VI-NEXT: {{ $}} 73 ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 74 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 75 ; VI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 76 ; VI-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 77 ; 78 ; GFX9-LABEL: name: fneg_s32_vv 79 ; GFX9: liveins: $vgpr0 80 ; GFX9-NEXT: {{ $}} 81 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 82 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 83 ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 84 ; GFX9-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 85 ; 86 ; GFX10-LABEL: name: fneg_s32_vv 87 ; GFX10: liveins: $vgpr0 88 ; GFX10-NEXT: {{ $}} 89 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 90 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 91 ; GFX10-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 92 ; GFX10-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 93 %0:vgpr(s32) = COPY $vgpr0 94 %1:vgpr(s32) = G_FNEG %0 95 $vgpr0 = COPY %1 96... 97 98--- 99name: fneg_s32_vs 100legalized: true 101regBankSelected: true 102tracksRegLiveness: true 103 104body: | 105 bb.0: 106 liveins: $sgpr0 107 ; SI-LABEL: name: fneg_s32_vs 108 ; SI: liveins: $sgpr0 109 ; SI-NEXT: {{ $}} 110 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 111 ; SI-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(s32) = G_FNEG [[COPY]] 112 ; SI-NEXT: $vgpr0 = COPY [[FNEG]](s32) 113 ; 114 ; VI-LABEL: name: fneg_s32_vs 115 ; VI: liveins: $sgpr0 116 ; VI-NEXT: {{ $}} 117 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 118 ; VI-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(s32) = G_FNEG [[COPY]] 119 ; VI-NEXT: $vgpr0 = COPY [[FNEG]](s32) 120 ; 121 ; GFX9-LABEL: name: fneg_s32_vs 122 ; GFX9: liveins: $sgpr0 123 ; GFX9-NEXT: {{ $}} 124 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 125 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(s32) = G_FNEG [[COPY]] 126 ; GFX9-NEXT: $vgpr0 = COPY [[FNEG]](s32) 127 ; 128 ; GFX10-LABEL: name: fneg_s32_vs 129 ; GFX10: liveins: $sgpr0 130 ; GFX10-NEXT: {{ $}} 131 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 132 ; GFX10-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(s32) = G_FNEG [[COPY]] 133 ; GFX10-NEXT: $vgpr0 = COPY [[FNEG]](s32) 134 %0:sgpr(s32) = COPY $sgpr0 135 %1:vgpr(s32) = G_FNEG %0 136 $vgpr0 = COPY %1 137... 138 139--- 140name: fneg_s16_ss 141legalized: true 142regBankSelected: true 143tracksRegLiveness: true 144 145body: | 146 bb.0: 147 liveins: $sgpr0 148 ; SI-LABEL: name: fneg_s16_ss 149 ; SI: liveins: $sgpr0 150 ; SI-NEXT: {{ $}} 151 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 152 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 153 ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 154 ; SI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 155 ; 156 ; VI-LABEL: name: fneg_s16_ss 157 ; VI: liveins: $sgpr0 158 ; VI-NEXT: {{ $}} 159 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 160 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 161 ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 162 ; VI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 163 ; 164 ; GFX9-LABEL: name: fneg_s16_ss 165 ; GFX9: liveins: $sgpr0 166 ; GFX9-NEXT: {{ $}} 167 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 168 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 169 ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 170 ; GFX9-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 171 ; 172 ; GFX10-LABEL: name: fneg_s16_ss 173 ; GFX10: liveins: $sgpr0 174 ; GFX10-NEXT: {{ $}} 175 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 176 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 177 ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 178 ; GFX10-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 179 %0:sgpr(s32) = COPY $sgpr0 180 %1:sgpr(s16) = G_TRUNC %0 181 %2:sgpr(s16) = G_FNEG %1 182 %3:sgpr(s32) = G_ANYEXT %2 183 $sgpr0 = COPY %3 184... 185 186--- 187name: fneg_s16_vv 188legalized: true 189regBankSelected: true 190tracksRegLiveness: true 191 192body: | 193 bb.0: 194 liveins: $vgpr0 195 ; SI-LABEL: name: fneg_s16_vv 196 ; SI: liveins: $vgpr0 197 ; SI-NEXT: {{ $}} 198 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 199 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 200 ; SI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 201 ; SI-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 202 ; 203 ; VI-LABEL: name: fneg_s16_vv 204 ; VI: liveins: $vgpr0 205 ; VI-NEXT: {{ $}} 206 ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 207 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 208 ; VI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 209 ; VI-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 210 ; 211 ; GFX9-LABEL: name: fneg_s16_vv 212 ; GFX9: liveins: $vgpr0 213 ; GFX9-NEXT: {{ $}} 214 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 215 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 216 ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 217 ; GFX9-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 218 ; 219 ; GFX10-LABEL: name: fneg_s16_vv 220 ; GFX10: liveins: $vgpr0 221 ; GFX10-NEXT: {{ $}} 222 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 223 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 224 ; GFX10-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 225 ; GFX10-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 226 %0:vgpr(s32) = COPY $vgpr0 227 %1:vgpr(s16) = G_TRUNC %0 228 %2:vgpr(s16) = G_FNEG %1 229 %3:vgpr(s32) = G_ANYEXT %2 230 $vgpr0 = COPY %3 231... 232 233--- 234name: fneg_s16_vs 235legalized: true 236regBankSelected: true 237tracksRegLiveness: true 238 239body: | 240 bb.0: 241 liveins: $sgpr0 242 243 ; SI-LABEL: name: fneg_s16_vs 244 ; SI: liveins: $sgpr0 245 ; SI-NEXT: {{ $}} 246 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 247 ; SI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 248 ; SI-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[TRUNC]] 249 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16) 250 ; SI-NEXT: $vgpr0 = COPY [[COPY1]](s32) 251 ; 252 ; VI-LABEL: name: fneg_s16_vs 253 ; VI: liveins: $sgpr0 254 ; VI-NEXT: {{ $}} 255 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 256 ; VI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 257 ; VI-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[TRUNC]] 258 ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16) 259 ; VI-NEXT: $vgpr0 = COPY [[COPY1]](s32) 260 ; 261 ; GFX9-LABEL: name: fneg_s16_vs 262 ; GFX9: liveins: $sgpr0 263 ; GFX9-NEXT: {{ $}} 264 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 265 ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 266 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[TRUNC]] 267 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16) 268 ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](s32) 269 ; 270 ; GFX10-LABEL: name: fneg_s16_vs 271 ; GFX10: liveins: $sgpr0 272 ; GFX10-NEXT: {{ $}} 273 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 274 ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 275 ; GFX10-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[TRUNC]] 276 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16) 277 ; GFX10-NEXT: $vgpr0 = COPY [[COPY1]](s32) 278 %0:sgpr(s32) = COPY $sgpr0 279 %1:sgpr(s16) = G_TRUNC %0 280 %2:vgpr(s16) = G_FNEG %1 281 %3:vgpr(s32) = G_ANYEXT %2 282 $vgpr0 = COPY %3 283... 284 285--- 286name: fneg_v2s16_ss 287legalized: true 288regBankSelected: true 289tracksRegLiveness: true 290 291body: | 292 bb.0: 293 liveins: $sgpr0_sgpr1 294 ; SI-LABEL: name: fneg_v2s16_ss 295 ; SI: liveins: $sgpr0_sgpr1 296 ; SI-NEXT: {{ $}} 297 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 298 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 299 ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 300 ; SI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 301 ; 302 ; VI-LABEL: name: fneg_v2s16_ss 303 ; VI: liveins: $sgpr0_sgpr1 304 ; VI-NEXT: {{ $}} 305 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 306 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 307 ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 308 ; VI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 309 ; 310 ; GFX9-LABEL: name: fneg_v2s16_ss 311 ; GFX9: liveins: $sgpr0_sgpr1 312 ; GFX9-NEXT: {{ $}} 313 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 314 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 315 ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 316 ; GFX9-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 317 ; 318 ; GFX10-LABEL: name: fneg_v2s16_ss 319 ; GFX10: liveins: $sgpr0_sgpr1 320 ; GFX10-NEXT: {{ $}} 321 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 322 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 323 ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 324 ; GFX10-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] 325 %0:sgpr(<2 x s16>) = COPY $sgpr0 326 %1:sgpr(<2 x s16>) = G_FNEG %0 327 $sgpr0 = COPY %1 328... 329 330--- 331name: fneg_v2s16_vv 332legalized: true 333regBankSelected: true 334tracksRegLiveness: true 335 336body: | 337 bb.0: 338 liveins: $vgpr0 339 ; SI-LABEL: name: fneg_v2s16_vv 340 ; SI: liveins: $vgpr0 341 ; SI-NEXT: {{ $}} 342 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 343 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 344 ; SI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 345 ; SI-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 346 ; 347 ; VI-LABEL: name: fneg_v2s16_vv 348 ; VI: liveins: $vgpr0 349 ; VI-NEXT: {{ $}} 350 ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 351 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 352 ; VI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 353 ; VI-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 354 ; 355 ; GFX9-LABEL: name: fneg_v2s16_vv 356 ; GFX9: liveins: $vgpr0 357 ; GFX9-NEXT: {{ $}} 358 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 359 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 360 ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 361 ; GFX9-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 362 ; 363 ; GFX10-LABEL: name: fneg_v2s16_vv 364 ; GFX10: liveins: $vgpr0 365 ; GFX10-NEXT: {{ $}} 366 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 367 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 368 ; GFX10-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 369 ; GFX10-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 370 %0:vgpr(<2 x s16>) = COPY $vgpr0 371 %1:vgpr(<2 x s16>) = G_FNEG %0 372 $vgpr0 = COPY %1 373... 374 375--- 376name: fneg_v2s16_vs 377legalized: true 378regBankSelected: true 379tracksRegLiveness: true 380 381body: | 382 bb.0: 383 liveins: $sgpr0 384 ; SI-LABEL: name: fneg_v2s16_vs 385 ; SI: liveins: $sgpr0 386 ; SI-NEXT: {{ $}} 387 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 388 ; SI-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FNEG [[COPY]] 389 ; SI-NEXT: $vgpr0 = COPY [[FNEG]](<2 x s16>) 390 ; 391 ; VI-LABEL: name: fneg_v2s16_vs 392 ; VI: liveins: $sgpr0 393 ; VI-NEXT: {{ $}} 394 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 395 ; VI-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FNEG [[COPY]] 396 ; VI-NEXT: $vgpr0 = COPY [[FNEG]](<2 x s16>) 397 ; 398 ; GFX9-LABEL: name: fneg_v2s16_vs 399 ; GFX9: liveins: $sgpr0 400 ; GFX9-NEXT: {{ $}} 401 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 402 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FNEG [[COPY]] 403 ; GFX9-NEXT: $vgpr0 = COPY [[FNEG]](<2 x s16>) 404 ; 405 ; GFX10-LABEL: name: fneg_v2s16_vs 406 ; GFX10: liveins: $sgpr0 407 ; GFX10-NEXT: {{ $}} 408 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 409 ; GFX10-NEXT: [[FNEG:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FNEG [[COPY]] 410 ; GFX10-NEXT: $vgpr0 = COPY [[FNEG]](<2 x s16>) 411 %0:sgpr(<2 x s16>) = COPY $sgpr0 412 %1:vgpr(<2 x s16>) = G_FNEG %0 413 $vgpr0 = COPY %1 414... 415 416--- 417name: fneg_s64_ss 418legalized: true 419regBankSelected: true 420tracksRegLiveness: true 421 422body: | 423 bb.0: 424 liveins: $sgpr0_sgpr1 425 ; SI-LABEL: name: fneg_s64_ss 426 ; SI: liveins: $sgpr0_sgpr1 427 ; SI-NEXT: {{ $}} 428 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 429 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 430 ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 431 ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 432 ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]] 433 ; SI-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 434 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 435 ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 436 ; 437 ; VI-LABEL: name: fneg_s64_ss 438 ; VI: liveins: $sgpr0_sgpr1 439 ; VI-NEXT: {{ $}} 440 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 441 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 442 ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 443 ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 444 ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]] 445 ; VI-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 446 ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 447 ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 448 ; 449 ; GFX9-LABEL: name: fneg_s64_ss 450 ; GFX9: liveins: $sgpr0_sgpr1 451 ; GFX9-NEXT: {{ $}} 452 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 453 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 454 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 455 ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 456 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]] 457 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 458 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 459 ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 460 ; 461 ; GFX10-LABEL: name: fneg_s64_ss 462 ; GFX10: liveins: $sgpr0_sgpr1 463 ; GFX10-NEXT: {{ $}} 464 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 465 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 466 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 467 ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 468 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]] 469 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 470 ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 471 ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 472 %0:sgpr(s64) = COPY $sgpr0_sgpr1 473 %1:sgpr(s64) = G_FNEG %0 474 S_ENDPGM 0, implicit %1 475... 476 477--- 478name: fneg_s64_vv 479legalized: true 480regBankSelected: true 481tracksRegLiveness: true 482 483body: | 484 bb.0: 485 liveins: $vgpr0_vgpr1 486 ; SI-LABEL: name: fneg_s64_vv 487 ; SI: liveins: $vgpr0_vgpr1 488 ; SI-NEXT: {{ $}} 489 ; SI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 490 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 491 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 492 ; SI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 493 ; SI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 494 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_XOR_B32_e64_]], %subreg.sub1 495 ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 496 ; 497 ; VI-LABEL: name: fneg_s64_vv 498 ; VI: liveins: $vgpr0_vgpr1 499 ; VI-NEXT: {{ $}} 500 ; VI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 501 ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 502 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 503 ; VI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 504 ; VI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 505 ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_XOR_B32_e64_]], %subreg.sub1 506 ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 507 ; 508 ; GFX9-LABEL: name: fneg_s64_vv 509 ; GFX9: liveins: $vgpr0_vgpr1 510 ; GFX9-NEXT: {{ $}} 511 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 512 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 513 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 514 ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 515 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 516 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_XOR_B32_e64_]], %subreg.sub1 517 ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 518 ; 519 ; GFX10-LABEL: name: fneg_s64_vv 520 ; GFX10: liveins: $vgpr0_vgpr1 521 ; GFX10-NEXT: {{ $}} 522 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 523 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 524 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 525 ; GFX10-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 526 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 527 ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_XOR_B32_e64_]], %subreg.sub1 528 ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 529 %0:vgpr(s64) = COPY $vgpr0_vgpr1 530 %1:vgpr(s64) = G_FNEG %0 531 S_ENDPGM 0, implicit %1 532... 533 534--- 535name: fneg_s64_vs 536legalized: true 537regBankSelected: true 538tracksRegLiveness: true 539 540body: | 541 bb.0: 542 liveins: $sgpr0_sgpr1 543 ; SI-LABEL: name: fneg_s64_vs 544 ; SI: liveins: $sgpr0_sgpr1 545 ; SI-NEXT: {{ $}} 546 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 547 ; SI-NEXT: [[FNEG:%[0-9]+]]:vgpr(s64) = G_FNEG [[COPY]] 548 ; SI-NEXT: S_ENDPGM 0, implicit [[FNEG]](s64) 549 ; 550 ; VI-LABEL: name: fneg_s64_vs 551 ; VI: liveins: $sgpr0_sgpr1 552 ; VI-NEXT: {{ $}} 553 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 554 ; VI-NEXT: [[FNEG:%[0-9]+]]:vgpr(s64) = G_FNEG [[COPY]] 555 ; VI-NEXT: S_ENDPGM 0, implicit [[FNEG]](s64) 556 ; 557 ; GFX9-LABEL: name: fneg_s64_vs 558 ; GFX9: liveins: $sgpr0_sgpr1 559 ; GFX9-NEXT: {{ $}} 560 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 561 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:vgpr(s64) = G_FNEG [[COPY]] 562 ; GFX9-NEXT: S_ENDPGM 0, implicit [[FNEG]](s64) 563 ; 564 ; GFX10-LABEL: name: fneg_s64_vs 565 ; GFX10: liveins: $sgpr0_sgpr1 566 ; GFX10-NEXT: {{ $}} 567 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 568 ; GFX10-NEXT: [[FNEG:%[0-9]+]]:vgpr(s64) = G_FNEG [[COPY]] 569 ; GFX10-NEXT: S_ENDPGM 0, implicit [[FNEG]](s64) 570 %0:sgpr(s64) = COPY $sgpr0_sgpr1 571 %1:vgpr(s64) = G_FNEG %0 572 S_ENDPGM 0, implicit %1 573 574... 575 576--- 577name: fneg_fabs_s32_ss 578legalized: true 579regBankSelected: true 580tracksRegLiveness: true 581 582body: | 583 bb.0: 584 liveins: $sgpr0_sgpr1 585 ; SI-LABEL: name: fneg_fabs_s32_ss 586 ; SI: liveins: $sgpr0_sgpr1 587 ; SI-NEXT: {{ $}} 588 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 589 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 590 ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 591 ; SI-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]] 592 ; 593 ; VI-LABEL: name: fneg_fabs_s32_ss 594 ; VI: liveins: $sgpr0_sgpr1 595 ; VI-NEXT: {{ $}} 596 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 597 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 598 ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 599 ; VI-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]] 600 ; 601 ; GFX9-LABEL: name: fneg_fabs_s32_ss 602 ; GFX9: liveins: $sgpr0_sgpr1 603 ; GFX9-NEXT: {{ $}} 604 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 605 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 606 ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 607 ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]] 608 ; 609 ; GFX10-LABEL: name: fneg_fabs_s32_ss 610 ; GFX10: liveins: $sgpr0_sgpr1 611 ; GFX10-NEXT: {{ $}} 612 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 613 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 614 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 615 ; GFX10-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]] 616 %0:sgpr(s32) = COPY $sgpr0 617 %1:sgpr(s32) = G_FABS %0 618 %2:sgpr(s32) = G_FNEG %1 619 S_ENDPGM 0, implicit %2 620... 621 622--- 623name: fneg_fabs_s32_vv 624legalized: true 625regBankSelected: true 626tracksRegLiveness: true 627 628body: | 629 bb.0: 630 liveins: $vgpr0 631 ; SI-LABEL: name: fneg_fabs_s32_vv 632 ; SI: liveins: $vgpr0 633 ; SI-NEXT: {{ $}} 634 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 635 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 636 ; SI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 637 ; SI-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]] 638 ; 639 ; VI-LABEL: name: fneg_fabs_s32_vv 640 ; VI: liveins: $vgpr0 641 ; VI-NEXT: {{ $}} 642 ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 643 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 644 ; VI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 645 ; VI-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]] 646 ; 647 ; GFX9-LABEL: name: fneg_fabs_s32_vv 648 ; GFX9: liveins: $vgpr0 649 ; GFX9-NEXT: {{ $}} 650 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 651 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 652 ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 653 ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]] 654 ; 655 ; GFX10-LABEL: name: fneg_fabs_s32_vv 656 ; GFX10: liveins: $vgpr0 657 ; GFX10-NEXT: {{ $}} 658 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 659 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 660 ; GFX10-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 661 ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]] 662 %0:vgpr(s32) = COPY $vgpr0 663 %1:vgpr(s32) = G_FABS %0 664 %2:vgpr(s32) = G_FNEG %0 665 S_ENDPGM 0, implicit %2 666... 667 668--- 669name: fneg_fabs_s32_vs 670legalized: true 671regBankSelected: true 672tracksRegLiveness: true 673 674body: | 675 bb.0: 676 liveins: $sgpr0 677 ; SI-LABEL: name: fneg_fabs_s32_vs 678 ; SI: liveins: $sgpr0 679 ; SI-NEXT: {{ $}} 680 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 681 ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]] 682 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147483648 683 ; SI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(s32) = V_XOR_B32_e64 [[S_MOV_B32_]](s16), [[FABS]](s32), implicit $exec 684 ; SI-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]](s32) 685 ; 686 ; VI-LABEL: name: fneg_fabs_s32_vs 687 ; VI: liveins: $sgpr0 688 ; VI-NEXT: {{ $}} 689 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 690 ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]] 691 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147483648 692 ; VI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(s32) = V_XOR_B32_e64 [[S_MOV_B32_]](s16), [[FABS]](s32), implicit $exec 693 ; VI-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]](s32) 694 ; 695 ; GFX9-LABEL: name: fneg_fabs_s32_vs 696 ; GFX9: liveins: $sgpr0 697 ; GFX9-NEXT: {{ $}} 698 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 699 ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]] 700 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147483648 701 ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(s32) = V_XOR_B32_e64 [[S_MOV_B32_]](s16), [[FABS]](s32), implicit $exec 702 ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]](s32) 703 ; 704 ; GFX10-LABEL: name: fneg_fabs_s32_vs 705 ; GFX10: liveins: $sgpr0 706 ; GFX10-NEXT: {{ $}} 707 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 708 ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]] 709 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147483648 710 ; GFX10-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(s32) = V_XOR_B32_e64 [[S_MOV_B32_]](s16), [[FABS]](s32), implicit $exec 711 ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]](s32) 712 %0:sgpr(s32) = COPY $sgpr0 713 %1:vgpr(s32) = G_FABS %0 714 %2:vgpr(s32) = G_FNEG %1 715 S_ENDPGM 0, implicit %2 716... 717 718--- 719name: fneg_fabs_s16_ss 720legalized: true 721regBankSelected: true 722tracksRegLiveness: true 723 724body: | 725 bb.0: 726 liveins: $sgpr0 727 ; SI-LABEL: name: fneg_fabs_s16_ss 728 ; SI: liveins: $sgpr0 729 ; SI-NEXT: {{ $}} 730 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 731 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 732 ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 733 ; SI-NEXT: $sgpr0 = COPY [[S_OR_B32_]] 734 ; 735 ; VI-LABEL: name: fneg_fabs_s16_ss 736 ; VI: liveins: $sgpr0 737 ; VI-NEXT: {{ $}} 738 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 739 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 740 ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 741 ; VI-NEXT: $sgpr0 = COPY [[S_OR_B32_]] 742 ; 743 ; GFX9-LABEL: name: fneg_fabs_s16_ss 744 ; GFX9: liveins: $sgpr0 745 ; GFX9-NEXT: {{ $}} 746 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 747 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 748 ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 749 ; GFX9-NEXT: $sgpr0 = COPY [[S_OR_B32_]] 750 ; 751 ; GFX10-LABEL: name: fneg_fabs_s16_ss 752 ; GFX10: liveins: $sgpr0 753 ; GFX10-NEXT: {{ $}} 754 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 755 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 756 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 757 ; GFX10-NEXT: $sgpr0 = COPY [[S_OR_B32_]] 758 %0:sgpr(s32) = COPY $sgpr0 759 %1:sgpr(s16) = G_TRUNC %0 760 %2:sgpr(s16) = G_FABS %1 761 %3:sgpr(s16) = G_FNEG %2 762 %4:sgpr(s32) = G_ANYEXT %3 763 $sgpr0 = COPY %4 764... 765 766--- 767name: fneg_fabs_s16_vv 768legalized: true 769regBankSelected: true 770tracksRegLiveness: true 771 772body: | 773 bb.0: 774 liveins: $vgpr0 775 ; SI-LABEL: name: fneg_fabs_s16_vv 776 ; SI: liveins: $vgpr0 777 ; SI-NEXT: {{ $}} 778 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 779 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 780 ; SI-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 781 ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_OR_B32_e64_]] 782 ; SI-NEXT: $vgpr0 = COPY [[COPY1]] 783 ; 784 ; VI-LABEL: name: fneg_fabs_s16_vv 785 ; VI: liveins: $vgpr0 786 ; VI-NEXT: {{ $}} 787 ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 788 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 789 ; VI-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 790 ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_OR_B32_e64_]] 791 ; VI-NEXT: $vgpr0 = COPY [[COPY1]] 792 ; 793 ; GFX9-LABEL: name: fneg_fabs_s16_vv 794 ; GFX9: liveins: $vgpr0 795 ; GFX9-NEXT: {{ $}} 796 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 797 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 798 ; GFX9-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 799 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_OR_B32_e64_]] 800 ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]] 801 ; 802 ; GFX10-LABEL: name: fneg_fabs_s16_vv 803 ; GFX10: liveins: $vgpr0 804 ; GFX10-NEXT: {{ $}} 805 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 806 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 807 ; GFX10-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 808 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_OR_B32_e64_]] 809 ; GFX10-NEXT: $vgpr0 = COPY [[COPY1]] 810 %0:vgpr(s32) = COPY $vgpr0 811 %1:vgpr(s16) = G_TRUNC %0 812 %2:vgpr(s16) = G_FABS %1 813 %3:vgpr(s16) = G_FNEG %2 814 %4:sgpr(s32) = G_ANYEXT %3 815 $vgpr0 = COPY %4 816... 817 818--- 819name: fneg_fabs_s16_vs 820legalized: true 821regBankSelected: true 822tracksRegLiveness: true 823 824body: | 825 bb.0: 826 liveins: $sgpr0 827 828 ; SI-LABEL: name: fneg_fabs_s16_vs 829 ; SI: liveins: $sgpr0 830 ; SI-NEXT: {{ $}} 831 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 832 ; SI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 833 ; SI-NEXT: [[FNEG:%[0-9]+]]:sgpr(s16) = G_FNEG [[TRUNC]] 834 ; SI-NEXT: [[FNEG1:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FNEG]] 835 ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FNEG1]](s16) 836 ; SI-NEXT: $vgpr0 = COPY [[COPY1]](s32) 837 ; 838 ; VI-LABEL: name: fneg_fabs_s16_vs 839 ; VI: liveins: $sgpr0 840 ; VI-NEXT: {{ $}} 841 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 842 ; VI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 843 ; VI-NEXT: [[FNEG:%[0-9]+]]:sgpr(s16) = G_FNEG [[TRUNC]] 844 ; VI-NEXT: [[FNEG1:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FNEG]] 845 ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FNEG1]](s16) 846 ; VI-NEXT: $vgpr0 = COPY [[COPY1]](s32) 847 ; 848 ; GFX9-LABEL: name: fneg_fabs_s16_vs 849 ; GFX9: liveins: $sgpr0 850 ; GFX9-NEXT: {{ $}} 851 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 852 ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 853 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:sgpr(s16) = G_FNEG [[TRUNC]] 854 ; GFX9-NEXT: [[FNEG1:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FNEG]] 855 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FNEG1]](s16) 856 ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](s32) 857 ; 858 ; GFX10-LABEL: name: fneg_fabs_s16_vs 859 ; GFX10: liveins: $sgpr0 860 ; GFX10-NEXT: {{ $}} 861 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 862 ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 863 ; GFX10-NEXT: [[FNEG:%[0-9]+]]:sgpr(s16) = G_FNEG [[TRUNC]] 864 ; GFX10-NEXT: [[FNEG1:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FNEG]] 865 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FNEG1]](s16) 866 ; GFX10-NEXT: $vgpr0 = COPY [[COPY1]](s32) 867 %0:sgpr(s32) = COPY $sgpr0 868 %1:sgpr(s16) = G_TRUNC %0 869 %2:sgpr(s16) = G_FNEG %1 870 %3:vgpr(s16) = G_FNEG %2 871 %4:sgpr(s32) = G_ANYEXT %3 872 $vgpr0 = COPY %4 873... 874 875--- 876name: fneg_fabs_v2s16_ss 877legalized: true 878regBankSelected: true 879tracksRegLiveness: true 880 881body: | 882 bb.0: 883 liveins: $sgpr0_sgpr1 884 ; SI-LABEL: name: fneg_fabs_v2s16_ss 885 ; SI: liveins: $sgpr0_sgpr1 886 ; SI-NEXT: {{ $}} 887 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 888 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 889 ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 890 ; SI-NEXT: $sgpr0 = COPY [[S_OR_B32_]] 891 ; 892 ; VI-LABEL: name: fneg_fabs_v2s16_ss 893 ; VI: liveins: $sgpr0_sgpr1 894 ; VI-NEXT: {{ $}} 895 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 896 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 897 ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 898 ; VI-NEXT: $sgpr0 = COPY [[S_OR_B32_]] 899 ; 900 ; GFX9-LABEL: name: fneg_fabs_v2s16_ss 901 ; GFX9: liveins: $sgpr0_sgpr1 902 ; GFX9-NEXT: {{ $}} 903 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 904 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 905 ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 906 ; GFX9-NEXT: $sgpr0 = COPY [[S_OR_B32_]] 907 ; 908 ; GFX10-LABEL: name: fneg_fabs_v2s16_ss 909 ; GFX10: liveins: $sgpr0_sgpr1 910 ; GFX10-NEXT: {{ $}} 911 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 912 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 913 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 914 ; GFX10-NEXT: $sgpr0 = COPY [[S_OR_B32_]] 915 %0:sgpr(<2 x s16>) = COPY $sgpr0 916 %1:sgpr(<2 x s16>) = G_FABS %0 917 %2:sgpr(<2 x s16>) = G_FNEG %1 918 $sgpr0 = COPY %2 919... 920 921--- 922name: fneg_fabs_v2s16_vv 923legalized: true 924regBankSelected: true 925tracksRegLiveness: true 926 927body: | 928 bb.0: 929 liveins: $vgpr0 930 ; SI-LABEL: name: fneg_fabs_v2s16_vv 931 ; SI: liveins: $vgpr0 932 ; SI-NEXT: {{ $}} 933 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 934 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 935 ; SI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 936 ; SI-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 937 ; 938 ; VI-LABEL: name: fneg_fabs_v2s16_vv 939 ; VI: liveins: $vgpr0 940 ; VI-NEXT: {{ $}} 941 ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 942 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 943 ; VI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 944 ; VI-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 945 ; 946 ; GFX9-LABEL: name: fneg_fabs_v2s16_vv 947 ; GFX9: liveins: $vgpr0 948 ; GFX9-NEXT: {{ $}} 949 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 950 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 951 ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 952 ; GFX9-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 953 ; 954 ; GFX10-LABEL: name: fneg_fabs_v2s16_vv 955 ; GFX10: liveins: $vgpr0 956 ; GFX10-NEXT: {{ $}} 957 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 958 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 959 ; GFX10-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 960 ; GFX10-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]] 961 %0:vgpr(<2 x s16>) = COPY $vgpr0 962 %1:vgpr(<2 x s16>) = G_FABS %0 963 %2:vgpr(<2 x s16>) = G_FNEG %0 964 $vgpr0 = COPY %2 965... 966 967--- 968name: fneg_fabs_v2s16_vs 969legalized: true 970regBankSelected: true 971tracksRegLiveness: true 972 973body: | 974 bb.0: 975 liveins: $sgpr0 976 ; SI-LABEL: name: fneg_fabs_v2s16_vs 977 ; SI: liveins: $sgpr0 978 ; SI-NEXT: {{ $}} 979 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 980 ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]] 981 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147516416 982 ; SI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(<2 x s16>) = V_XOR_B32_e64 [[S_MOV_B32_]](s16), [[FABS]](<2 x s16>), implicit $exec 983 ; SI-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]](<2 x s16>) 984 ; 985 ; VI-LABEL: name: fneg_fabs_v2s16_vs 986 ; VI: liveins: $sgpr0 987 ; VI-NEXT: {{ $}} 988 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 989 ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]] 990 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147516416 991 ; VI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(<2 x s16>) = V_XOR_B32_e64 [[S_MOV_B32_]](s16), [[FABS]](<2 x s16>), implicit $exec 992 ; VI-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]](<2 x s16>) 993 ; 994 ; GFX9-LABEL: name: fneg_fabs_v2s16_vs 995 ; GFX9: liveins: $sgpr0 996 ; GFX9-NEXT: {{ $}} 997 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 998 ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]] 999 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147516416 1000 ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(<2 x s16>) = V_XOR_B32_e64 [[S_MOV_B32_]](s16), [[FABS]](<2 x s16>), implicit $exec 1001 ; GFX9-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]](<2 x s16>) 1002 ; 1003 ; GFX10-LABEL: name: fneg_fabs_v2s16_vs 1004 ; GFX10: liveins: $sgpr0 1005 ; GFX10-NEXT: {{ $}} 1006 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 1007 ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]] 1008 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147516416 1009 ; GFX10-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(<2 x s16>) = V_XOR_B32_e64 [[S_MOV_B32_]](s16), [[FABS]](<2 x s16>), implicit $exec 1010 ; GFX10-NEXT: $vgpr0 = COPY [[V_XOR_B32_e64_]](<2 x s16>) 1011 %0:sgpr(<2 x s16>) = COPY $sgpr0 1012 %1:vgpr(<2 x s16>) = G_FABS %0 1013 %2:vgpr(<2 x s16>) = G_FNEG %1 1014 $vgpr0 = COPY %2 1015... 1016 1017--- 1018name: fneg_fabs_s64_ss 1019legalized: true 1020regBankSelected: true 1021tracksRegLiveness: true 1022 1023body: | 1024 bb.0: 1025 liveins: $sgpr0_sgpr1 1026 ; SI-LABEL: name: fneg_fabs_s64_ss 1027 ; SI: liveins: $sgpr0_sgpr1 1028 ; SI-NEXT: {{ $}} 1029 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 1030 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 1031 ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 1032 ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 1033 ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]] 1034 ; SI-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 1035 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 1036 ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 1037 ; 1038 ; VI-LABEL: name: fneg_fabs_s64_ss 1039 ; VI: liveins: $sgpr0_sgpr1 1040 ; VI-NEXT: {{ $}} 1041 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 1042 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 1043 ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 1044 ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 1045 ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]] 1046 ; VI-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 1047 ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 1048 ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 1049 ; 1050 ; GFX9-LABEL: name: fneg_fabs_s64_ss 1051 ; GFX9: liveins: $sgpr0_sgpr1 1052 ; GFX9-NEXT: {{ $}} 1053 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 1054 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 1055 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 1056 ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 1057 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]] 1058 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 1059 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 1060 ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 1061 ; 1062 ; GFX10-LABEL: name: fneg_fabs_s64_ss 1063 ; GFX10: liveins: $sgpr0_sgpr1 1064 ; GFX10-NEXT: {{ $}} 1065 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 1066 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 1067 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 1068 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 1069 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]] 1070 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 1071 ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 1072 ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 1073 %0:sgpr(s64) = COPY $sgpr0_sgpr1 1074 %1:sgpr(s64) = G_FABS %0 1075 %2:sgpr(s64) = G_FNEG %1 1076 S_ENDPGM 0, implicit %2 1077... 1078 1079--- 1080name: fneg_fabs_s64_vv 1081legalized: true 1082regBankSelected: true 1083tracksRegLiveness: true 1084 1085body: | 1086 bb.0: 1087 liveins: $vgpr0_vgpr1 1088 ; SI-LABEL: name: fneg_fabs_s64_vv 1089 ; SI: liveins: $vgpr0_vgpr1 1090 ; SI-NEXT: {{ $}} 1091 ; SI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 1092 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 1093 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 1094 ; SI-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 1095 ; SI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 1096 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_OR_B32_e64_]], %subreg.sub1 1097 ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 1098 ; 1099 ; VI-LABEL: name: fneg_fabs_s64_vv 1100 ; VI: liveins: $vgpr0_vgpr1 1101 ; VI-NEXT: {{ $}} 1102 ; VI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 1103 ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 1104 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 1105 ; VI-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 1106 ; VI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 1107 ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_OR_B32_e64_]], %subreg.sub1 1108 ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 1109 ; 1110 ; GFX9-LABEL: name: fneg_fabs_s64_vv 1111 ; GFX9: liveins: $vgpr0_vgpr1 1112 ; GFX9-NEXT: {{ $}} 1113 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 1114 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 1115 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 1116 ; GFX9-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 1117 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 1118 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_OR_B32_e64_]], %subreg.sub1 1119 ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 1120 ; 1121 ; GFX10-LABEL: name: fneg_fabs_s64_vv 1122 ; GFX10: liveins: $vgpr0_vgpr1 1123 ; GFX10-NEXT: {{ $}} 1124 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 1125 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 1126 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 1127 ; GFX10-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 1128 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 1129 ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_OR_B32_e64_]], %subreg.sub1 1130 ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 1131 %0:vgpr(s64) = COPY $vgpr0_vgpr1 1132 %1:vgpr(s64) = G_FABS %0 1133 %2:vgpr(s64) = G_FNEG %1 1134 S_ENDPGM 0, implicit %2 1135... 1136 1137--- 1138name: fneg_fabs_s64_vs 1139legalized: true 1140regBankSelected: true 1141tracksRegLiveness: true 1142 1143body: | 1144 bb.0: 1145 liveins: $sgpr0_sgpr1 1146 ; SI-LABEL: name: fneg_fabs_s64_vs 1147 ; SI: liveins: $sgpr0_sgpr1 1148 ; SI-NEXT: {{ $}} 1149 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 1150 ; SI-NEXT: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]] 1151 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub1(s64) 1152 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s32) = S_MOV_B32 2147483648 1153 ; SI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(s16) = V_XOR_B32_e64 [[S_MOV_B32_]](s32), [[COPY1]](s32), implicit $exec 1154 ; SI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub0(s64) 1155 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64(s64) = REG_SEQUENCE [[COPY2]](s32), %subreg.sub0, [[V_XOR_B32_e64_]](s16), %subreg.sub1 1156 ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]](s64) 1157 ; 1158 ; VI-LABEL: name: fneg_fabs_s64_vs 1159 ; VI: liveins: $sgpr0_sgpr1 1160 ; VI-NEXT: {{ $}} 1161 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 1162 ; VI-NEXT: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]] 1163 ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub1(s64) 1164 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s32) = S_MOV_B32 2147483648 1165 ; VI-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(s16) = V_XOR_B32_e64 [[S_MOV_B32_]](s32), [[COPY1]](s32), implicit $exec 1166 ; VI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub0(s64) 1167 ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64(s64) = REG_SEQUENCE [[COPY2]](s32), %subreg.sub0, [[V_XOR_B32_e64_]](s16), %subreg.sub1 1168 ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]](s64) 1169 ; 1170 ; GFX9-LABEL: name: fneg_fabs_s64_vs 1171 ; GFX9: liveins: $sgpr0_sgpr1 1172 ; GFX9-NEXT: {{ $}} 1173 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 1174 ; GFX9-NEXT: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]] 1175 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub1(s64) 1176 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s32) = S_MOV_B32 2147483648 1177 ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(s16) = V_XOR_B32_e64 [[S_MOV_B32_]](s32), [[COPY1]](s32), implicit $exec 1178 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub0(s64) 1179 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64(s64) = REG_SEQUENCE [[COPY2]](s32), %subreg.sub0, [[V_XOR_B32_e64_]](s16), %subreg.sub1 1180 ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]](s64) 1181 ; 1182 ; GFX10-LABEL: name: fneg_fabs_s64_vs 1183 ; GFX10: liveins: $sgpr0_sgpr1 1184 ; GFX10-NEXT: {{ $}} 1185 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 1186 ; GFX10-NEXT: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]] 1187 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub1(s64) 1188 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s32) = S_MOV_B32 2147483648 1189 ; GFX10-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32(s16) = V_XOR_B32_e64 [[S_MOV_B32_]](s32), [[COPY1]](s32), implicit $exec 1190 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub0(s64) 1191 ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64(s64) = REG_SEQUENCE [[COPY2]](s32), %subreg.sub0, [[V_XOR_B32_e64_]](s16), %subreg.sub1 1192 ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]](s64) 1193 %0:sgpr(s64) = COPY $sgpr0_sgpr1 1194 %1:vgpr(s64) = G_FABS %0 1195 %2:vgpr(s64) = G_FNEG %1 1196 S_ENDPGM 0, implicit %2 1197... 1198