xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir (revision 8871c3c562690347d75190be758312d1f92a7db4)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX7 %s
3
4# FIXME: Ideally this would fail to select with ieee mode enabled.
5---
6
7name: fminnum_f32_f64_ieee_mode_on
8legalized:       true
9regBankSelected: true
10machineFunctionInfo:
11  mode:
12    ieee: true
13
14body: |
15  bb.0:
16    liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
17    ; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_on
18    ; GFX7: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
19    ; GFX7-NEXT: {{  $}}
20    ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
21    ; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
22    ; GFX7-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
23    ; GFX7-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
24    ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
25    ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
26    ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
27    ; GFX7-NEXT: %7:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
28    ; GFX7-NEXT: %8:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
29    ; GFX7-NEXT: %9:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
30    ; GFX7-NEXT: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
31    ; GFX7-NEXT: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
32    ; GFX7-NEXT: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
33    ; GFX7-NEXT: %10:vreg_64 = nofpexcept V_MIN_F64_e64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
34    ; GFX7-NEXT: %11:vreg_64 = nofpexcept V_MIN_F64_e64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
35    ; GFX7-NEXT: %12:vreg_64 = nofpexcept V_MIN_F64_e64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
36    ; GFX7-NEXT: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
37    %0:sgpr(s32) = COPY $sgpr0
38    %1:vgpr(s32) = COPY $vgpr0
39    %2:vgpr(s32) = COPY $vgpr1
40    %3:vgpr(p1) = COPY $vgpr3_vgpr4
41
42    %10:sgpr(s64) = COPY $sgpr10_sgpr11
43    %11:vgpr(s64) = COPY $vgpr10_vgpr11
44    %12:vgpr(s64) = COPY $vgpr12_vgpr13
45
46    ; minnum vs
47    %4:vgpr(s32) = G_FMINNUM %1, %0
48
49    ; minnum sv
50    %5:vgpr(s32) = G_FMINNUM %0, %1
51
52    ; minnum vv
53    %6:vgpr(s32) = G_FMINNUM %1, %2
54
55    G_STORE %4, %3 :: (store (s32), addrspace 1)
56    G_STORE %5, %3 :: (store (s32), addrspace 1)
57    G_STORE %6, %3 :: (store (s32), addrspace 1)
58
59    ; 64-bit
60
61    ; minnum vs
62    %14:vgpr(s64) = G_FMINNUM %10, %11
63
64    ; minnum sv
65    %15:vgpr(s64) = G_FMINNUM %11, %10
66
67    ; minnum vv
68    %16:vgpr(s64) = G_FMINNUM %11, %12
69
70    S_ENDPGM 0, implicit %14, implicit %15, implicit %16
71...
72
73---
74
75name: fminnum_f32_f64_ieee_mode_off
76legalized:       true
77regBankSelected: true
78machineFunctionInfo:
79  mode:
80    ieee: false
81
82body: |
83  bb.0:
84    liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
85    ; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_off
86    ; GFX7: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
87    ; GFX7-NEXT: {{  $}}
88    ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
89    ; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
90    ; GFX7-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
91    ; GFX7-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
92    ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
93    ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
94    ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
95    ; GFX7-NEXT: %7:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
96    ; GFX7-NEXT: %8:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
97    ; GFX7-NEXT: %9:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
98    ; GFX7-NEXT: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
99    ; GFX7-NEXT: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
100    ; GFX7-NEXT: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
101    ; GFX7-NEXT: %10:vreg_64 = nofpexcept V_MIN_F64_e64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
102    ; GFX7-NEXT: %11:vreg_64 = nofpexcept V_MIN_F64_e64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
103    ; GFX7-NEXT: %12:vreg_64 = nofpexcept V_MIN_F64_e64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
104    ; GFX7-NEXT: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
105    %0:sgpr(s32) = COPY $sgpr0
106    %1:vgpr(s32) = COPY $vgpr0
107    %2:vgpr(s32) = COPY $vgpr1
108    %3:vgpr(p1) = COPY $vgpr3_vgpr4
109
110    %10:sgpr(s64) = COPY $sgpr10_sgpr11
111    %11:vgpr(s64) = COPY $vgpr10_vgpr11
112    %12:vgpr(s64) = COPY $vgpr12_vgpr13
113
114    ; minnum vs
115    %4:vgpr(s32) = G_FMINNUM %1, %0
116
117    ; minnum sv
118    %5:vgpr(s32) = G_FMINNUM %0, %1
119
120    ; minnum vv
121    %6:vgpr(s32) = G_FMINNUM %1, %2
122
123    G_STORE %4, %3 :: (store (s32), addrspace 1)
124    G_STORE %5, %3 :: (store (s32), addrspace 1)
125    G_STORE %6, %3 :: (store (s32), addrspace 1)
126
127    ; 64-bit
128
129    ; minnum vs
130    %14:vgpr(s64) = G_FMINNUM %10, %11
131
132    ; minnum sv
133    %15:vgpr(s64) = G_FMINNUM %11, %10
134
135    ; minnum vv
136    %16:vgpr(s64) = G_FMINNUM %11, %12
137
138    S_ENDPGM 0, implicit %14, implicit %15, implicit %16
139...
140