xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=CHECK %s
3# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=CHECK %s
4# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=CHECK %s
5# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX11 %s
6
7---
8name: fminnum_ieee_f16_vv
9legalized: true
10regBankSelected: true
11
12body: |
13  bb.0:
14    liveins: $vgpr0, $vgpr1
15
16    ; CHECK-LABEL: name: fminnum_ieee_f16_vv
17    ; CHECK: liveins: $vgpr0, $vgpr1
18    ; CHECK-NEXT: {{  $}}
19    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
20    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
21    ; CHECK-NEXT: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
22    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]]
23    ;
24    ; GFX11-LABEL: name: fminnum_ieee_f16_vv
25    ; GFX11: liveins: $vgpr0, $vgpr1
26    ; GFX11-NEXT: {{  $}}
27    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
28    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
29    ; GFX11-NEXT: [[V_MIN_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MIN_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
30    ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_MIN_F16_fake16_e64_]]
31    %0:vgpr(s32) = COPY $vgpr0
32    %1:vgpr(s32) = COPY $vgpr1
33    %2:vgpr(s16) = G_TRUNC %0
34    %3:vgpr(s16) = G_TRUNC %1
35    %4:vgpr(s16) = G_FMINNUM_IEEE %2, %3
36    S_ENDPGM 0, implicit %4
37...
38
39---
40name: fminnum_ieee_f16_v_fneg_v
41legalized: true
42regBankSelected: true
43
44body: |
45  bb.0:
46    liveins: $vgpr0, $vgpr1
47
48    ; CHECK-LABEL: name: fminnum_ieee_f16_v_fneg_v
49    ; CHECK: liveins: $vgpr0, $vgpr1
50    ; CHECK-NEXT: {{  $}}
51    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
52    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
53    ; CHECK-NEXT: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec
54    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]]
55    ;
56    ; GFX11-LABEL: name: fminnum_ieee_f16_v_fneg_v
57    ; GFX11: liveins: $vgpr0, $vgpr1
58    ; GFX11-NEXT: {{  $}}
59    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
60    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
61    ; GFX11-NEXT: [[V_MIN_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MIN_F16_fake16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec
62    ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_MIN_F16_fake16_e64_]]
63    %0:vgpr(s32) = COPY $vgpr0
64    %1:vgpr(s32) = COPY $vgpr1
65    %2:vgpr(s16) = G_TRUNC %0
66    %3:vgpr(s16) = G_TRUNC %1
67    %4:vgpr(s16) = G_FNEG %3
68    %5:vgpr(s16) = G_FMINNUM_IEEE %2, %4
69    S_ENDPGM 0, implicit %5
70...
71