1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- 5name: fexp2_s16_vs 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9 10body: | 11 bb.0: 12 liveins: $sgpr0 13 14 ; CHECK-LABEL: name: fexp2_s16_vs 15 ; CHECK: liveins: $sgpr0 16 ; CHECK-NEXT: {{ $}} 17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 18 ; CHECK-NEXT: [[V_EXP_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec 19 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_EXP_F16_e64_]] 20 %0:sgpr(s32) = COPY $sgpr0 21 %1:sgpr(s16) = G_TRUNC %0 22 %2:vgpr(s16) = G_FEXP2 %1 23 S_ENDPGM 0, implicit %2 24... 25 26--- 27name: fexp2_s16_vv 28legalized: true 29regBankSelected: true 30tracksRegLiveness: true 31 32body: | 33 bb.0: 34 liveins: $vgpr0 35 36 ; CHECK-LABEL: name: fexp2_s16_vv 37 ; CHECK: liveins: $vgpr0 38 ; CHECK-NEXT: {{ $}} 39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 40 ; CHECK-NEXT: [[V_EXP_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec 41 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_EXP_F16_e64_]] 42 %0:vgpr(s32) = COPY $vgpr0 43 %1:vgpr(s16) = G_TRUNC %0 44 %2:vgpr(s16) = G_FEXP2 %1 45 S_ENDPGM 0, implicit %2 46... 47