1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s 3 4--- 5name: fconstant_v_s32 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9 10body: | 11 bb.0: 12 ; GCN-LABEL: name: fconstant_v_s32 13 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec 14 ; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec 15 ; GCN-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec 16 ; GCN-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec 17 ; GCN-NEXT: $vgpr0 = COPY [[V_MOV_B32_e32_]] 18 ; GCN-NEXT: $vgpr1 = COPY [[V_MOV_B32_e32_1]] 19 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]] 20 %0:vgpr(s32) = G_FCONSTANT float 1.0 21 %1:vgpr(s32) = G_FCONSTANT float 8.0 22 %2:vgpr(s32) = G_FCONSTANT float 1.0 23 %3:vgpr(s32) = G_FCONSTANT float 8.0 24 $vgpr0 = COPY %0 25 $vgpr1 = COPY %1 26 S_ENDPGM 0, implicit %2 , implicit %3 27... 28 29--- 30name: fconstant_s_s32 31legalized: true 32regBankSelected: true 33tracksRegLiveness: true 34 35body: | 36 bb.0: 37 ; GCN-LABEL: name: fconstant_s_s32 38 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1065353216 39 ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1090519040 40 ; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 3212836864 41 ; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 3238002688 42 ; GCN-NEXT: $sgpr0 = COPY [[S_MOV_B32_]] 43 ; GCN-NEXT: $sgpr1 = COPY [[S_MOV_B32_1]] 44 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]] 45 %0:sgpr(s32) = G_FCONSTANT float 1.0 46 %1:sgpr(s32) = G_FCONSTANT float 8.0 47 %2:sgpr(s32) = G_FCONSTANT float -1.0 48 %3:sgpr(s32) = G_FCONSTANT float -8.0 49 $sgpr0 = COPY %0 50 $sgpr1 = COPY %1 51 S_ENDPGM 0, implicit %2 , implicit %3 52 53... 54 55--- 56name: fconstant_v_s64 57legalized: true 58regBankSelected: true 59tracksRegLiveness: true 60 61body: | 62 bb.0: 63 ; GCN-LABEL: name: fconstant_v_s64 64 ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec 65 ; GCN-NEXT: [[V_MOV_B1:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 4620693217682128896, implicit $exec 66 ; GCN-NEXT: [[V_MOV_B2:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO -4611686018427387904, implicit $exec 67 ; GCN-NEXT: [[V_MOV_B3:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 4621819117588971520, implicit $exec 68 ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_MOV_B]] 69 ; GCN-NEXT: $vgpr2_vgpr3 = COPY [[V_MOV_B1]] 70 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B2]], implicit [[V_MOV_B3]] 71 %0:vgpr(s64) = G_FCONSTANT double 1.0 72 %1:vgpr(s64) = G_FCONSTANT double 8.0 73 %2:vgpr(s64) = G_FCONSTANT double -2.0 74 %3:vgpr(s64) = G_FCONSTANT double 10.0 75 $vgpr0_vgpr1 = COPY %0 76 $vgpr2_vgpr3 = COPY %1 77 S_ENDPGM 0, implicit %2 , implicit %3 78 79... 80 81--- 82name: fconstant_s_s64 83legalized: true 84regBankSelected: true 85tracksRegLiveness: true 86 87body: | 88 bb.0: 89 ; GCN-LABEL: name: fconstant_s_s64 90 ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 4607182418800017408 91 ; GCN-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4620693217682128896 92 ; GCN-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 -4611686018427387904 93 ; GCN-NEXT: [[S_MOV_B1:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -4601552919265804288 94 ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_MOV_B64_]] 95 ; GCN-NEXT: $sgpr2_sgpr3 = COPY [[S_MOV_B]] 96 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_MOV_B64_]], implicit [[S_MOV_B]], implicit [[S_MOV_B64_1]], implicit [[S_MOV_B1]] 97 %0:sgpr(s64) = G_FCONSTANT double 1.0 98 %1:sgpr(s64) = G_FCONSTANT double 8.0 99 %2:sgpr(s64) = G_FCONSTANT double -2.0 100 %3:sgpr(s64) = G_FCONSTANT double -10.0 101 $sgpr0_sgpr1 = COPY %0 102 $sgpr2_sgpr3 = COPY %1 103 S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2 , implicit %3 104... 105 106--- 107name: fconstant_v_s16 108legalized: true 109regBankSelected: true 110tracksRegLiveness: true 111 112body: | 113 bb.0: 114 ; GCN-LABEL: name: fconstant_v_s16 115 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 15360, implicit $exec 116 ; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 18432, implicit $exec 117 ; GCN-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 15360, implicit $exec 118 ; GCN-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 18432, implicit $exec 119 ; GCN-NEXT: $vgpr0 = COPY [[V_MOV_B32_e32_]] 120 ; GCN-NEXT: $vgpr1 = COPY [[V_MOV_B32_e32_1]] 121 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]] 122 %0:vgpr(s16) = G_FCONSTANT half 1.0 123 %1:vgpr(s16) = G_FCONSTANT half 8.0 124 %2:vgpr(s32) = G_ANYEXT %0 125 %3:vgpr(s32) = G_ANYEXT %1 126 127 %4:vgpr(s16) = G_FCONSTANT half 1.0 128 %5:vgpr(s16) = G_FCONSTANT half 8.0 129 $vgpr0 = COPY %2 130 $vgpr1 = COPY %3 131 S_ENDPGM 0, implicit %4, implicit %5 132 133... 134 135--- 136name: fconstant_s_s16 137legalized: true 138regBankSelected: true 139tracksRegLiveness: true 140 141body: | 142 bb.0: 143 ; GCN-LABEL: name: fconstant_s_s16 144 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15360 145 ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 18432 146 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] 147 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]] 148 ; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 15360 149 ; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 18432 150 ; GCN-NEXT: $sgpr0 = COPY [[COPY]] 151 ; GCN-NEXT: $sgpr1 = COPY [[COPY1]] 152 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]] 153 %0:sgpr(s16) = G_FCONSTANT half 1.0 154 %1:sgpr(s16) = G_FCONSTANT half 8.0 155 %2:vgpr(s32) = G_ANYEXT %0 156 %3:vgpr(s32) = G_ANYEXT %1 157 158 %4:sgpr(s16) = G_FCONSTANT half 1.0 159 %5:sgpr(s16) = G_FCONSTANT half 8.0 160 $sgpr0 = COPY %2 161 $sgpr1 = COPY %3 162 S_ENDPGM 0, implicit %4, implicit %5 163 164... 165