xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir (revision 1941f341722178390f71e07502e08a2250a704c7) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name: ctpop_s32_ss
6legalized: true
7regBankSelected: true
8tracksRegLiveness: true
9
10body: |
11  bb.0:
12    liveins: $sgpr0
13
14    ; CHECK-LABEL: name: ctpop_s32_ss
15    ; CHECK: liveins: $sgpr0
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
18    ; CHECK-NEXT: [[S_BCNT1_I32_B32_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B32 [[COPY]], implicit-def dead $scc
19    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_BCNT1_I32_B32_]]
20    %0:sgpr(s32) = COPY $sgpr0
21    %1:sgpr(s32) = G_CTPOP %0
22    S_ENDPGM 0, implicit %1
23...
24
25---
26name: ctpop_s32_vs
27legalized: true
28regBankSelected: true
29tracksRegLiveness: true
30
31body: |
32  bb.0:
33    liveins: $sgpr0
34
35    ; CHECK-LABEL: name: ctpop_s32_vs
36    ; CHECK: liveins: $sgpr0
37    ; CHECK-NEXT: {{  $}}
38    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
39    ; CHECK-NEXT: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], 0, implicit $exec
40    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
41    %0:sgpr(s32) = COPY $sgpr0
42    %1:vgpr(s32) = G_CTPOP %0
43    S_ENDPGM 0, implicit %1
44...
45
46---
47name: ctpop_s32_vv
48legalized: true
49regBankSelected: true
50tracksRegLiveness: true
51
52body: |
53  bb.0:
54    liveins: $vgpr0
55
56    ; CHECK-LABEL: name: ctpop_s32_vv
57    ; CHECK: liveins: $vgpr0
58    ; CHECK-NEXT: {{  $}}
59    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
60    ; CHECK-NEXT: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], 0, implicit $exec
61    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
62    %0:vgpr(s32) = COPY $vgpr0
63    %1:vgpr(s32) = G_CTPOP %0
64    S_ENDPGM 0, implicit %1
65...
66
67---
68name: add_ctpop_s32_v_vv_commute0
69legalized: true
70regBankSelected: true
71tracksRegLiveness: true
72
73body: |
74  bb.0:
75    liveins: $vgpr0, $vgpr1
76
77    ; CHECK-LABEL: name: add_ctpop_s32_v_vv_commute0
78    ; CHECK: liveins: $vgpr0, $vgpr1
79    ; CHECK-NEXT: {{  $}}
80    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
81    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
82    ; CHECK-NEXT: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
83    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
84    %0:vgpr(s32) = COPY $vgpr0
85    %1:vgpr(s32) = COPY $vgpr1
86    %2:vgpr(s32) = G_CTPOP %0
87    %3:vgpr(s32) = G_ADD %2, %1
88    S_ENDPGM 0, implicit %3
89...
90
91---
92name: add_ctpop_s32_v_vv_commute1
93legalized: true
94regBankSelected: true
95tracksRegLiveness: true
96
97body: |
98  bb.0:
99    liveins: $vgpr0, $vgpr1
100
101    ; CHECK-LABEL: name: add_ctpop_s32_v_vv_commute1
102    ; CHECK: liveins: $vgpr0, $vgpr1
103    ; CHECK-NEXT: {{  $}}
104    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
105    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
106    ; CHECK-NEXT: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
107    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
108    %0:vgpr(s32) = COPY $vgpr0
109    %1:vgpr(s32) = COPY $vgpr1
110    %2:vgpr(s32) = G_CTPOP %0
111    %3:vgpr(s32) = G_ADD %1, %2
112    S_ENDPGM 0, implicit %3
113...
114
115# Test add+ctpop pattern with all scalars. This should stay scalar.
116---
117name: add_ctpop_s32_s_ss_commute0
118legalized: true
119regBankSelected: true
120tracksRegLiveness: true
121
122body: |
123  bb.0:
124    liveins: $sgpr0, $sgpr1
125
126    ; CHECK-LABEL: name: add_ctpop_s32_s_ss_commute0
127    ; CHECK: liveins: $sgpr0, $sgpr1
128    ; CHECK-NEXT: {{  $}}
129    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
130    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
131    ; CHECK-NEXT: [[S_BCNT1_I32_B32_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B32 [[COPY]], implicit-def dead $scc
132    ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BCNT1_I32_B32_]], [[COPY1]], implicit-def dead $scc
133    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]]
134    %0:sgpr(s32) = COPY $sgpr0
135    %1:sgpr(s32) = COPY $sgpr1
136    %2:sgpr(s32) = G_CTPOP %0
137    %3:sgpr(s32) = G_ADD %2, %1
138    S_ENDPGM 0, implicit %3
139...
140
141---
142name: add_ctpop_s32_v_vs_commute0
143legalized: true
144regBankSelected: true
145tracksRegLiveness: true
146
147body: |
148  bb.0:
149    liveins: $vgpr0, $sgpr0
150
151    ; CHECK-LABEL: name: add_ctpop_s32_v_vs_commute0
152    ; CHECK: liveins: $vgpr0, $sgpr0
153    ; CHECK-NEXT: {{  $}}
154    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
155    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
156    ; CHECK-NEXT: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
157    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
158    %0:vgpr(s32) = COPY $vgpr0
159    %1:sgpr(s32) = COPY $sgpr0
160    %2:vgpr(s32) = G_CTPOP %0
161    %3:vgpr(s32) = G_ADD %2, %1
162    S_ENDPGM 0, implicit %3
163...
164
165# SGPR->VGPR ctpop with VALU add
166---
167name: add_ctpop_s32_v_sv_commute0
168legalized: true
169regBankSelected: true
170tracksRegLiveness: true
171
172body: |
173  bb.0:
174    liveins: $vgpr0, $sgpr0
175
176    ; CHECK-LABEL: name: add_ctpop_s32_v_sv_commute0
177    ; CHECK: liveins: $vgpr0, $sgpr0
178    ; CHECK-NEXT: {{  $}}
179    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
180    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
181    ; CHECK-NEXT: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY1]], [[COPY]], implicit $exec
182    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
183    %0:vgpr(s32) = COPY $vgpr0
184    %1:sgpr(s32) = COPY $sgpr0
185    %2:vgpr(s32) = G_CTPOP %1
186    %3:vgpr(s32) = G_ADD %2, %0
187    S_ENDPGM 0, implicit %3
188...
189
190# Scalar ctpop with VALU add
191---
192name: add_ctpop_s32_s_sv_commute0
193legalized: true
194regBankSelected: true
195tracksRegLiveness: true
196
197body: |
198  bb.0:
199    liveins: $sgpr0, $vgpr0
200
201    ; CHECK-LABEL: name: add_ctpop_s32_s_sv_commute0
202    ; CHECK: liveins: $sgpr0, $vgpr0
203    ; CHECK-NEXT: {{  $}}
204    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
205    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
206    ; CHECK-NEXT: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
207    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
208    %0:sgpr(s32) = COPY $sgpr0
209    %1:vgpr(s32) = COPY $vgpr0
210    %2:sgpr(s32) = G_CTPOP %0
211    %3:vgpr(s32) = G_ADD %2, %1
212    S_ENDPGM 0, implicit %3
213...
214
215---
216name: ctpop_s64_ss
217legalized: true
218regBankSelected: true
219tracksRegLiveness: true
220
221body: |
222  bb.0:
223    liveins: $sgpr0_sgpr1
224
225    ; CHECK-LABEL: name: ctpop_s64_ss
226    ; CHECK: liveins: $sgpr0_sgpr1
227    ; CHECK-NEXT: {{  $}}
228    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
229    ; CHECK-NEXT: [[S_BCNT1_I32_B64_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B64 [[COPY]], implicit-def dead $scc
230    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_BCNT1_I32_B64_]]
231    %0:sgpr(s64) = COPY $sgpr0_sgpr1
232    %1:sgpr(s32) = G_CTPOP %0
233    S_ENDPGM 0, implicit %1
234...
235