xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir (revision 7b4c8b35d43c0a17f222722487d7a2b4ceee0a26) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
3# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
4# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
5# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX11 %s
6
7# Note: 16-bit instructions generally produce a 0 result in the high 16-bits on GFX8 and GFX9 and preserve high 16 bits on GFX10+
8
9---
10name:            add_s16
11legalized:       true
12regBankSelected: true
13tracksRegLiveness: true
14
15body: |
16  bb.0:
17    liveins: $vgpr0, $vgpr1
18
19    ; GFX6-LABEL: name: add_s16
20    ; GFX6: liveins: $vgpr0, $vgpr1
21    ; GFX6-NEXT: {{  $}}
22    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
23    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
24    ; GFX6-NEXT: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
25    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
26    ;
27    ; GFX10-LABEL: name: add_s16
28    ; GFX10: liveins: $vgpr0, $vgpr1
29    ; GFX10-NEXT: {{  $}}
30    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
31    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
32    ; GFX10-NEXT: [[V_ADD_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
33    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ADD_NC_U16_e64_]]
34    ;
35    ; GFX11-LABEL: name: add_s16
36    ; GFX11: liveins: $vgpr0, $vgpr1
37    ; GFX11-NEXT: {{  $}}
38    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
39    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
40    ; GFX11-NEXT: [[V_ADD_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
41    ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_ADD_NC_U16_fake16_e64_]]
42    %0:vgpr(s32) = COPY $vgpr0
43    %1:vgpr(s32) = COPY $vgpr1
44    %2:vgpr(s16) = G_TRUNC %0
45    %3:vgpr(s16) = G_TRUNC %1
46    %4:vgpr(s16) = G_ADD %2, %3
47    S_ENDPGM 0, implicit %4
48
49...
50
51---
52name:            add_s16_zext_to_s32
53legalized:       true
54regBankSelected: true
55tracksRegLiveness: true
56
57body: |
58  bb.0:
59    liveins: $vgpr0, $vgpr1
60
61    ; GFX6-LABEL: name: add_s16_zext_to_s32
62    ; GFX6: liveins: $vgpr0, $vgpr1
63    ; GFX6-NEXT: {{  $}}
64    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
65    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
66    ; GFX6-NEXT: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
67    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
68    ;
69    ; GFX10-LABEL: name: add_s16_zext_to_s32
70    ; GFX10: liveins: $vgpr0, $vgpr1
71    ; GFX10-NEXT: {{  $}}
72    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
73    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
74    ; GFX10-NEXT: [[V_ADD_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
75    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
76    ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_ADD_NC_U16_e64_]], implicit $exec
77    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
78    ;
79    ; GFX11-LABEL: name: add_s16_zext_to_s32
80    ; GFX11: liveins: $vgpr0, $vgpr1
81    ; GFX11-NEXT: {{  $}}
82    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
83    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
84    ; GFX11-NEXT: [[V_ADD_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
85    ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
86    ; GFX11-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_ADD_NC_U16_fake16_e64_]], implicit $exec
87    ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
88    %0:vgpr(s32) = COPY $vgpr0
89    %1:vgpr(s32) = COPY $vgpr1
90    %2:vgpr(s16) = G_TRUNC %0
91    %3:vgpr(s16) = G_TRUNC %1
92    %4:vgpr(s16) = G_ADD %2, %3
93    %5:vgpr(s32) = G_ZEXT %4
94    S_ENDPGM 0, implicit %5
95
96...
97
98---
99name:            add_s16_neg_inline_const_64
100legalized:       true
101regBankSelected: true
102tracksRegLiveness: true
103
104body: |
105  bb.0:
106    liveins: $vgpr0
107
108    ; GFX6-LABEL: name: add_s16_neg_inline_const_64
109    ; GFX6: liveins: $vgpr0
110    ; GFX6-NEXT: {{  $}}
111    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
112    ; GFX6-NEXT: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
113    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
114    ;
115    ; GFX10-LABEL: name: add_s16_neg_inline_const_64
116    ; GFX10: liveins: $vgpr0
117    ; GFX10-NEXT: {{  $}}
118    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
119    ; GFX10-NEXT: [[V_SUB_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec
120    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_SUB_NC_U16_e64_]]
121    ;
122    ; GFX11-LABEL: name: add_s16_neg_inline_const_64
123    ; GFX11: liveins: $vgpr0
124    ; GFX11-NEXT: {{  $}}
125    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
126    ; GFX11-NEXT: [[V_SUB_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_fake16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec
127    ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_SUB_NC_U16_fake16_e64_]]
128    %0:vgpr(s32) = COPY $vgpr0
129    %1:vgpr(s16) = G_TRUNC %0
130    %2:vgpr(s16) = G_CONSTANT i16 -64
131    %3:vgpr(s16) = G_ADD %1, %2
132    S_ENDPGM 0, implicit %3
133
134...
135
136---
137name:            add_s16_neg_inline_const_64_zext_to_s32
138legalized:       true
139regBankSelected: true
140tracksRegLiveness: true
141
142body: |
143  bb.0:
144    liveins: $vgpr0
145
146    ; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
147    ; GFX6: liveins: $vgpr0
148    ; GFX6-NEXT: {{  $}}
149    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
150    ; GFX6-NEXT: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
151    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
152    ;
153    ; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
154    ; GFX10: liveins: $vgpr0
155    ; GFX10-NEXT: {{  $}}
156    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
157    ; GFX10-NEXT: [[V_SUB_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec
158    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
159    ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_SUB_NC_U16_e64_]], implicit $exec
160    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
161    ;
162    ; GFX11-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
163    ; GFX11: liveins: $vgpr0
164    ; GFX11-NEXT: {{  $}}
165    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
166    ; GFX11-NEXT: [[V_SUB_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_fake16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec
167    ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
168    ; GFX11-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_SUB_NC_U16_fake16_e64_]], implicit $exec
169    ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
170    %0:vgpr(s32) = COPY $vgpr0
171    %1:vgpr(s16) = G_TRUNC %0
172    %2:vgpr(s16) = G_CONSTANT i16 -64
173    %3:vgpr(s16) = G_ADD %1, %2
174    %4:vgpr(s32) = G_ZEXT %3
175    S_ENDPGM 0, implicit %4
176
177...
178