xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir (revision b60c118f53e6f7e5328e54dc26b4d6787030c02b) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
3
4---
5name: divergent_i1_phi_if_then
6legalized: true
7tracksRegLiveness: true
8body: |
9  ; GFX10-LABEL: name: divergent_i1_phi_if_then
10  ; GFX10: bb.0:
11  ; GFX10-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
12  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
13  ; GFX10-NEXT: {{  $}}
14  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
15  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
16  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
17  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
18  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
19  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
20  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]]
21  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
22  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C1]]
23  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)
24  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[COPY4]](s1)
25  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
26  ; GFX10-NEXT:   G_BR %bb.1
27  ; GFX10-NEXT: {{  $}}
28  ; GFX10-NEXT: bb.1:
29  ; GFX10-NEXT:   successors: %bb.2(0x80000000)
30  ; GFX10-NEXT: {{  $}}
31  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
32  ; GFX10-NEXT:   [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]]
33  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)
34  ; GFX10-NEXT:   [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc
35  ; GFX10-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY6]](s1), implicit-def $scc
36  ; GFX10-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
37  ; GFX10-NEXT: {{  $}}
38  ; GFX10-NEXT: bb.2:
39  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY4]](s1), %bb.0, [[S_OR_B32_]](s1), %bb.1
40  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
41  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
42  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
43  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
44  ; GFX10-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY7]](s1), [[C4]], [[C3]]
45  ; GFX10-NEXT:   G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)
46  ; GFX10-NEXT:   S_ENDPGM 0
47  bb.0:
48    successors: %bb.1(0x40000000), %bb.2(0x40000000)
49    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
50
51    %0:_(s32) = COPY $vgpr0
52    %1:_(s32) = COPY $vgpr1
53    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
54    %3:_(s32) = COPY $vgpr2
55    %4:_(s32) = COPY $vgpr3
56    %5:_(s32) = G_CONSTANT i32 6
57    %6:_(s1) = G_ICMP intpred(uge), %3(s32), %5
58    %7:_(s32) = G_CONSTANT i32 0
59    %8:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %4(s32), %7
60    %9:sreg_32_xm0_xexec(s32) = SI_IF %8(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
61    G_BR %bb.1
62
63  bb.1:
64    successors: %bb.2(0x80000000)
65
66    %10:_(s32) = G_CONSTANT i32 1
67    %11:_(s1) = G_ICMP intpred(ult), %3(s32), %10
68
69  bb.2:
70    %12:_(s1) = G_PHI %6(s1), %bb.0, %11(s1), %bb.1
71    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %9(s32)
72    %13:_(s32) = G_CONSTANT i32 2
73    %14:_(s32) = G_CONSTANT i32 1
74    %15:_(s32) = G_SELECT %12(s1), %14, %13
75    G_STORE %15(s32), %2(p1) :: (store (s32), addrspace 1)
76    S_ENDPGM 0
77...
78
79---
80name: divergent_i1_phi_if_else
81legalized: true
82tracksRegLiveness: true
83body: |
84  ; GFX10-LABEL: name: divergent_i1_phi_if_else
85  ; GFX10: bb.0:
86  ; GFX10-NEXT:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
87  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
88  ; GFX10-NEXT: {{  $}}
89  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
90  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
91  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
92  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
93  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
94  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
95  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
96  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C]]
97  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[DEF]](s1)
98  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[COPY4]](s1)
99  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
100  ; GFX10-NEXT:   G_BR %bb.3
101  ; GFX10-NEXT: {{  $}}
102  ; GFX10-NEXT: bb.1:
103  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
104  ; GFX10-NEXT: {{  $}}
105  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY4]](s1), %bb.0, %20(s1), %bb.3
106  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
107  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[COPY6]](s1)
108  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[COPY7]](s1)
109  ; GFX10-NEXT:   [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_ELSE [[SI_IF]](s32), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
110  ; GFX10-NEXT:   G_BR %bb.2
111  ; GFX10-NEXT: {{  $}}
112  ; GFX10-NEXT: bb.2:
113  ; GFX10-NEXT:   successors: %bb.4(0x80000000)
114  ; GFX10-NEXT: {{  $}}
115  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
116  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C1]]
117  ; GFX10-NEXT:   [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP1]](s1)
118  ; GFX10-NEXT:   [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc
119  ; GFX10-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc
120  ; GFX10-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
121  ; GFX10-NEXT:   G_BR %bb.4
122  ; GFX10-NEXT: {{  $}}
123  ; GFX10-NEXT: bb.3:
124  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
125  ; GFX10-NEXT: {{  $}}
126  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
127  ; GFX10-NEXT:   [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]]
128  ; GFX10-NEXT:   [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)
129  ; GFX10-NEXT:   [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc
130  ; GFX10-NEXT:   [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY10]](s1), implicit-def $scc
131  ; GFX10-NEXT:   [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
132  ; GFX10-NEXT:   G_BR %bb.1
133  ; GFX10-NEXT: {{  $}}
134  ; GFX10-NEXT: bb.4:
135  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[COPY7]](s1), %bb.1, [[S_OR_B32_]](s1), %bb.2
136  ; GFX10-NEXT:   [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
137  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_ELSE]](s32)
138  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
139  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
140  ; GFX10-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY11]](s1), [[C3]], [[C4]]
141  ; GFX10-NEXT:   G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)
142  ; GFX10-NEXT:   S_ENDPGM 0
143  bb.0:
144    successors: %bb.3(0x40000000), %bb.1(0x40000000)
145    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
146
147    %0:_(s32) = COPY $vgpr0
148    %1:_(s32) = COPY $vgpr1
149    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
150    %3:_(s32) = COPY $vgpr2
151    %4:_(s32) = COPY $vgpr3
152    %5:_(s1) = G_IMPLICIT_DEF
153    %6:_(s32) = G_CONSTANT i32 0
154    %7:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %4(s32), %6
155    %8:sreg_32_xm0_xexec(s32) = SI_IF %7(s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
156    G_BR %bb.3
157
158  bb.1:
159    successors: %bb.2(0x40000000), %bb.4(0x40000000)
160
161    %9:_(s1) = G_PHI %10(s1), %bb.3, %5(s1), %bb.0
162    %11:sreg_32_xm0_xexec(s32) = SI_ELSE %8(s32), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
163    G_BR %bb.2
164
165  bb.2:
166    successors: %bb.4(0x80000000)
167
168    %12:_(s32) = G_CONSTANT i32 1
169    %13:_(s1) = G_ICMP intpred(uge), %3(s32), %12
170    G_BR %bb.4
171
172  bb.3:
173    successors: %bb.1(0x80000000)
174
175    %14:_(s32) = G_CONSTANT i32 2
176    %10:_(s1) = G_ICMP intpred(ult), %3(s32), %14
177    G_BR %bb.1
178
179  bb.4:
180    %15:_(s1) = G_PHI %9(s1), %bb.1, %13(s1), %bb.2
181    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %11(s32)
182    %16:_(s32) = G_CONSTANT i32 1
183    %17:_(s32) = G_CONSTANT i32 2
184    %18:_(s32) = G_SELECT %15(s1), %16, %17
185    G_STORE %18(s32), %2(p1) :: (store (s32), addrspace 1)
186    S_ENDPGM 0
187...
188
189---
190name: loop_with_1break
191legalized: true
192tracksRegLiveness: true
193body: |
194  ; GFX10-LABEL: name: loop_with_1break
195  ; GFX10: bb.0:
196  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
197  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
198  ; GFX10-NEXT: {{  $}}
199  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
200  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
201  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
202  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
203  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
204  ; GFX10-NEXT:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
205  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
206  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
207  ; GFX10-NEXT:   [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
208  ; GFX10-NEXT: {{  $}}
209  ; GFX10-NEXT: bb.1:
210  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
211  ; GFX10-NEXT: {{  $}}
212  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %35(s1), %bb.3
213  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.3, [[C]](s32), %bb.0
214  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %11(s32), %bb.3
215  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
216  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
217  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)
218  ; GFX10-NEXT:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI2]](s32)
219  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
220  ; GFX10-NEXT:   [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
221  ; GFX10-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)
222  ; GFX10-NEXT:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
223  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
224  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
225  ; GFX10-NEXT:   [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY4]](s1), $exec_lo, implicit-def $scc
226  ; GFX10-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY5]](s1), implicit-def $scc
227  ; GFX10-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
228  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
229  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
230  ; GFX10-NEXT:   G_BR %bb.2
231  ; GFX10-NEXT: {{  $}}
232  ; GFX10-NEXT: bb.2:
233  ; GFX10-NEXT:   successors: %bb.3(0x80000000)
234  ; GFX10-NEXT: {{  $}}
235  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
236  ; GFX10-NEXT:   [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C4]](s32)
237  ; GFX10-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64)
238  ; GFX10-NEXT:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)
239  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
240  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C5]]
241  ; GFX10-NEXT:   G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1)
242  ; GFX10-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C5]]
243  ; GFX10-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
244  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI2]](s32), [[C6]]
245  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP1]](s1)
246  ; GFX10-NEXT:   [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc
247  ; GFX10-NEXT:   [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY7]](s1), implicit-def $scc
248  ; GFX10-NEXT:   [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
249  ; GFX10-NEXT: {{  $}}
250  ; GFX10-NEXT: bb.3:
251  ; GFX10-NEXT:   successors: %bb.4(0x04000000), %bb.1(0x7c000000)
252  ; GFX10-NEXT: {{  $}}
253  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, [[S_OR_B32_1]](s1), %bb.2
254  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.2, [[DEF]](s32), %bb.1
255  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)
256  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
257  ; GFX10-NEXT:   [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY8]](s1), [[PHI1]](s32)
258  ; GFX10-NEXT:   SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
259  ; GFX10-NEXT:   G_BR %bb.4
260  ; GFX10-NEXT: {{  $}}
261  ; GFX10-NEXT: bb.4:
262  ; GFX10-NEXT:   [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.3
263  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI5]](s32)
264  ; GFX10-NEXT:   S_ENDPGM 0
265  bb.0:
266    successors: %bb.1(0x80000000)
267    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
268
269    %0:_(s32) = COPY $vgpr0
270    %1:_(s32) = COPY $vgpr1
271    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
272    %3:_(s32) = COPY $vgpr2
273    %4:_(s32) = COPY $vgpr3
274    %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)
275    %6:_(s32) = G_CONSTANT i32 0
276    %7:_(s32) = G_IMPLICIT_DEF
277
278  bb.1:
279    successors: %bb.2(0x40000000), %bb.3(0x40000000)
280
281    %8:_(s32) = G_PHI %9(s32), %bb.3, %6(s32), %bb.0
282    %10:_(s32) = G_PHI %6(s32), %bb.0, %11(s32), %bb.3
283    %12:_(s1) = G_CONSTANT i1 true
284    %13:_(s64) = G_SEXT %10(s32)
285    %14:_(s32) = G_CONSTANT i32 2
286    %15:_(s64) = G_SHL %13, %14(s32)
287    %16:_(p1) = G_PTR_ADD %5, %15(s64)
288    %17:_(s32) = G_LOAD %16(p1) :: (load (s32), addrspace 1)
289    %18:_(s32) = G_CONSTANT i32 0
290    %19:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %17(s32), %18
291    %20:sreg_32_xm0_xexec(s32) = SI_IF %19(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
292    G_BR %bb.2
293
294  bb.2:
295    successors: %bb.3(0x80000000)
296
297    %21:_(s32) = G_CONSTANT i32 2
298    %22:_(s64) = G_SHL %13, %21(s32)
299    %23:_(p1) = G_PTR_ADD %2, %22(s64)
300    %24:_(s32) = G_LOAD %23(p1) :: (load (s32), addrspace 1)
301    %25:_(s32) = G_CONSTANT i32 1
302    %26:_(s32) = G_ADD %24, %25
303    G_STORE %26(s32), %23(p1) :: (store (s32), addrspace 1)
304    %27:_(s32) = G_ADD %10, %25
305    %28:_(s32) = G_CONSTANT i32 100
306    %29:_(s1) = G_ICMP intpred(ult), %10(s32), %28
307
308  bb.3:
309    successors: %bb.4(0x04000000), %bb.1(0x7c000000)
310
311    %11:_(s32) = G_PHI %27(s32), %bb.2, %7(s32), %bb.1
312    %30:_(s1) = G_PHI %29(s1), %bb.2, %12(s1), %bb.1
313    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %20(s32)
314    %9:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %30(s1), %8(s32)
315    SI_LOOP %9(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
316    G_BR %bb.4
317
318  bb.4:
319    %31:_(s32) = G_PHI %9(s32), %bb.3
320    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %31(s32)
321    S_ENDPGM 0
322...
323
324---
325name: loop_with_2breaks
326legalized: true
327tracksRegLiveness: true
328body: |
329  ; GFX10-LABEL: name: loop_with_2breaks
330  ; GFX10: bb.0:
331  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
332  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
333  ; GFX10-NEXT: {{  $}}
334  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
335  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
336  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
337  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
338  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
339  ; GFX10-NEXT:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
340  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
341  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
342  ; GFX10-NEXT:   [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
343  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
344  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
345  ; GFX10-NEXT:   [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
346  ; GFX10-NEXT: {{  $}}
347  ; GFX10-NEXT: bb.1:
348  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
349  ; GFX10-NEXT: {{  $}}
350  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %48(s1), %bb.3
351  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.3, [[C]](s32), %bb.0
352  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.3
353  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
354  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
355  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)
356  ; GFX10-NEXT:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI2]](s32)
357  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
358  ; GFX10-NEXT:   [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
359  ; GFX10-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)
360  ; GFX10-NEXT:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
361  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
362  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
363  ; GFX10-NEXT:   [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc
364  ; GFX10-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY7]](s1), implicit-def $scc
365  ; GFX10-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
366  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
367  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
368  ; GFX10-NEXT:   G_BR %bb.2
369  ; GFX10-NEXT: {{  $}}
370  ; GFX10-NEXT: bb.2:
371  ; GFX10-NEXT:   successors: %bb.4(0x40000000), %bb.5(0x40000000)
372  ; GFX10-NEXT: {{  $}}
373  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
374  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
375  ; GFX10-NEXT:   [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C5]](s32)
376  ; GFX10-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV2]], [[SHL1]](s64)
377  ; GFX10-NEXT:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)
378  ; GFX10-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
379  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD1]](s32), [[C6]]
380  ; GFX10-NEXT:   [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C4]](s1)
381  ; GFX10-NEXT:   [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[COPY9]](s1)
382  ; GFX10-NEXT:   [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
383  ; GFX10-NEXT:   G_BR %bb.4
384  ; GFX10-NEXT: {{  $}}
385  ; GFX10-NEXT: bb.3:
386  ; GFX10-NEXT:   successors: %bb.6(0x04000000), %bb.1(0x7c000000)
387  ; GFX10-NEXT: {{  $}}
388  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, %47(s1), %bb.5
389  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI %32(s32), %bb.5, [[DEF]](s32), %bb.1
390  ; GFX10-NEXT:   [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)
391  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
392  ; GFX10-NEXT:   [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY11]](s1), [[PHI1]](s32)
393  ; GFX10-NEXT:   SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
394  ; GFX10-NEXT:   G_BR %bb.6
395  ; GFX10-NEXT: {{  $}}
396  ; GFX10-NEXT: bb.4:
397  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
398  ; GFX10-NEXT: {{  $}}
399  ; GFX10-NEXT:   [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
400  ; GFX10-NEXT:   [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C7]](s32)
401  ; GFX10-NEXT:   [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL2]](s64)
402  ; GFX10-NEXT:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s32), addrspace 1)
403  ; GFX10-NEXT:   [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
404  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[C8]]
405  ; GFX10-NEXT:   G_STORE [[ADD]](s32), [[PTR_ADD2]](p1) :: (store (s32), addrspace 1)
406  ; GFX10-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C8]]
407  ; GFX10-NEXT:   [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
408  ; GFX10-NEXT:   [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI2]](s32), [[C9]]
409  ; GFX10-NEXT:   [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)
410  ; GFX10-NEXT:   [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc
411  ; GFX10-NEXT:   [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY12]](s1), implicit-def $scc
412  ; GFX10-NEXT:   [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
413  ; GFX10-NEXT: {{  $}}
414  ; GFX10-NEXT: bb.5:
415  ; GFX10-NEXT:   successors: %bb.3(0x80000000)
416  ; GFX10-NEXT: {{  $}}
417  ; GFX10-NEXT:   [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[COPY9]](s1), %bb.2, [[S_OR_B32_1]](s1), %bb.4
418  ; GFX10-NEXT:   [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.4, [[DEF]](s32), %bb.2
419  ; GFX10-NEXT:   [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)
420  ; GFX10-NEXT:   [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[COPY13]](s1)
421  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32)
422  ; GFX10-NEXT:   [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc
423  ; GFX10-NEXT:   [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY14]](s1), implicit-def $scc
424  ; GFX10-NEXT:   [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc
425  ; GFX10-NEXT:   G_BR %bb.3
426  ; GFX10-NEXT: {{  $}}
427  ; GFX10-NEXT: bb.6:
428  ; GFX10-NEXT:   [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.3
429  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI7]](s32)
430  ; GFX10-NEXT:   S_ENDPGM 0
431  bb.0:
432    successors: %bb.1(0x80000000)
433    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
434
435    %0:_(s32) = COPY $vgpr0
436    %1:_(s32) = COPY $vgpr1
437    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
438    %3:_(s32) = COPY $vgpr2
439    %4:_(s32) = COPY $vgpr3
440    %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)
441    %6:_(s32) = COPY $vgpr4
442    %7:_(s32) = COPY $vgpr5
443    %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)
444    %9:_(s32) = G_CONSTANT i32 0
445    %10:_(s32) = G_IMPLICIT_DEF
446
447  bb.1:
448    successors: %bb.2(0x40000000), %bb.3(0x40000000)
449
450    %11:_(s32) = G_PHI %12(s32), %bb.3, %9(s32), %bb.0
451    %13:_(s32) = G_PHI %9(s32), %bb.0, %14(s32), %bb.3
452    %15:_(s1) = G_CONSTANT i1 true
453    %16:_(s64) = G_SEXT %13(s32)
454    %17:_(s32) = G_CONSTANT i32 2
455    %18:_(s64) = G_SHL %16, %17(s32)
456    %19:_(p1) = G_PTR_ADD %5, %18(s64)
457    %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1)
458    %21:_(s32) = G_CONSTANT i32 0
459    %22:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %20(s32), %21
460    %23:sreg_32_xm0_xexec(s32) = SI_IF %22(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
461    G_BR %bb.2
462
463  bb.2:
464    successors: %bb.4(0x40000000), %bb.5(0x40000000)
465
466    %24:_(s1) = G_CONSTANT i1 true
467    %25:_(s32) = G_CONSTANT i32 2
468    %26:_(s64) = G_SHL %16, %25(s32)
469    %27:_(p1) = G_PTR_ADD %8, %26(s64)
470    %28:_(s32) = G_LOAD %27(p1) :: (load (s32), addrspace 1)
471    %29:_(s32) = G_CONSTANT i32 0
472    %30:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %28(s32), %29
473    %31:sreg_32_xm0_xexec(s32) = SI_IF %30(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
474    G_BR %bb.4
475
476  bb.3:
477    successors: %bb.6(0x04000000), %bb.1(0x7c000000)
478
479    %14:_(s32) = G_PHI %32(s32), %bb.5, %10(s32), %bb.1
480    %33:_(s1) = G_PHI %34(s1), %bb.5, %15(s1), %bb.1
481    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32)
482    %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %33(s1), %11(s32)
483    SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
484    G_BR %bb.6
485
486  bb.4:
487    successors: %bb.5(0x80000000)
488
489    %35:_(s32) = G_CONSTANT i32 2
490    %36:_(s64) = G_SHL %16, %35(s32)
491    %37:_(p1) = G_PTR_ADD %2, %36(s64)
492    %38:_(s32) = G_LOAD %37(p1) :: (load (s32), addrspace 1)
493    %39:_(s32) = G_CONSTANT i32 1
494    %40:_(s32) = G_ADD %38, %39
495    G_STORE %40(s32), %37(p1) :: (store (s32), addrspace 1)
496    %41:_(s32) = G_ADD %13, %39
497    %42:_(s32) = G_CONSTANT i32 100
498    %43:_(s1) = G_ICMP intpred(ult), %13(s32), %42
499
500  bb.5:
501    successors: %bb.3(0x80000000)
502
503    %32:_(s32) = G_PHI %41(s32), %bb.4, %10(s32), %bb.2
504    %34:_(s1) = G_PHI %43(s1), %bb.4, %24(s1), %bb.2
505    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %31(s32)
506    G_BR %bb.3
507
508  bb.6:
509    %44:_(s32) = G_PHI %12(s32), %bb.3
510    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %44(s32)
511    S_ENDPGM 0
512...
513
514---
515name: loop_with_3breaks
516legalized: true
517tracksRegLiveness: true
518body: |
519  ; GFX10-LABEL: name: loop_with_3breaks
520  ; GFX10: bb.0:
521  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
522  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
523  ; GFX10-NEXT: {{  $}}
524  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
525  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
526  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
527  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
528  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
529  ; GFX10-NEXT:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
530  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
531  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
532  ; GFX10-NEXT:   [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
533  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
534  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
535  ; GFX10-NEXT:   [[MV3:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
536  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
537  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
538  ; GFX10-NEXT:   [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
539  ; GFX10-NEXT: {{  $}}
540  ; GFX10-NEXT: bb.1:
541  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
542  ; GFX10-NEXT: {{  $}}
543  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %61(s1), %bb.3
544  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s32) = G_PHI %15(s32), %bb.3, [[C]](s32), %bb.0
545  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %17(s32), %bb.3
546  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
547  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
548  ; GFX10-NEXT:   [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)
549  ; GFX10-NEXT:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI2]](s32)
550  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
551  ; GFX10-NEXT:   [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
552  ; GFX10-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)
553  ; GFX10-NEXT:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
554  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
555  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
556  ; GFX10-NEXT:   [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc
557  ; GFX10-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc
558  ; GFX10-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
559  ; GFX10-NEXT:   [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
560  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
561  ; GFX10-NEXT:   G_BR %bb.2
562  ; GFX10-NEXT: {{  $}}
563  ; GFX10-NEXT: bb.2:
564  ; GFX10-NEXT:   successors: %bb.4(0x40000000), %bb.5(0x40000000)
565  ; GFX10-NEXT: {{  $}}
566  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
567  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
568  ; GFX10-NEXT:   [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C5]](s32)
569  ; GFX10-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV2]], [[SHL1]](s64)
570  ; GFX10-NEXT:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)
571  ; GFX10-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
572  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD1]](s32), [[C6]]
573  ; GFX10-NEXT:   [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[C4]](s1)
574  ; GFX10-NEXT:   [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[COPY11]](s1)
575  ; GFX10-NEXT:   [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
576  ; GFX10-NEXT:   G_BR %bb.4
577  ; GFX10-NEXT: {{  $}}
578  ; GFX10-NEXT: bb.3:
579  ; GFX10-NEXT:   successors: %bb.8(0x04000000), %bb.1(0x7c000000)
580  ; GFX10-NEXT: {{  $}}
581  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, %60(s1), %bb.5
582  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI %35(s32), %bb.5, [[DEF]](s32), %bb.1
583  ; GFX10-NEXT:   [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)
584  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
585  ; GFX10-NEXT:   [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY13]](s1), [[PHI1]](s32)
586  ; GFX10-NEXT:   SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
587  ; GFX10-NEXT:   G_BR %bb.8
588  ; GFX10-NEXT: {{  $}}
589  ; GFX10-NEXT: bb.4:
590  ; GFX10-NEXT:   successors: %bb.6(0x40000000), %bb.7(0x40000000)
591  ; GFX10-NEXT: {{  $}}
592  ; GFX10-NEXT:   [[C7:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
593  ; GFX10-NEXT:   [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
594  ; GFX10-NEXT:   [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C8]](s32)
595  ; GFX10-NEXT:   [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV3]], [[SHL2]](s64)
596  ; GFX10-NEXT:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s32), addrspace 1)
597  ; GFX10-NEXT:   [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
598  ; GFX10-NEXT:   [[ICMP2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD2]](s32), [[C9]]
599  ; GFX10-NEXT:   [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[C7]](s1)
600  ; GFX10-NEXT:   [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[COPY14]](s1)
601  ; GFX10-NEXT:   [[SI_IF2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP2]](s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
602  ; GFX10-NEXT:   G_BR %bb.6
603  ; GFX10-NEXT: {{  $}}
604  ; GFX10-NEXT: bb.5:
605  ; GFX10-NEXT:   successors: %bb.3(0x80000000)
606  ; GFX10-NEXT: {{  $}}
607  ; GFX10-NEXT:   [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[COPY11]](s1), %bb.2, %72(s1), %bb.7
608  ; GFX10-NEXT:   [[PHI6:%[0-9]+]]:_(s32) = G_PHI %46(s32), %bb.7, [[DEF]](s32), %bb.2
609  ; GFX10-NEXT:   [[COPY16:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)
610  ; GFX10-NEXT:   [[COPY17:%[0-9]+]]:sreg_32(s1) = COPY [[COPY16]](s1)
611  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32)
612  ; GFX10-NEXT:   [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc
613  ; GFX10-NEXT:   [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY17]](s1), implicit-def $scc
614  ; GFX10-NEXT:   [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
615  ; GFX10-NEXT:   G_BR %bb.3
616  ; GFX10-NEXT: {{  $}}
617  ; GFX10-NEXT: bb.6:
618  ; GFX10-NEXT:   successors: %bb.7(0x80000000)
619  ; GFX10-NEXT: {{  $}}
620  ; GFX10-NEXT:   [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
621  ; GFX10-NEXT:   [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C10]](s32)
622  ; GFX10-NEXT:   [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL3]](s64)
623  ; GFX10-NEXT:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s32), addrspace 1)
624  ; GFX10-NEXT:   [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
625  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[C11]]
626  ; GFX10-NEXT:   G_STORE [[ADD]](s32), [[PTR_ADD3]](p1) :: (store (s32), addrspace 1)
627  ; GFX10-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C11]]
628  ; GFX10-NEXT:   [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
629  ; GFX10-NEXT:   [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI2]](s32), [[C12]]
630  ; GFX10-NEXT:   [[COPY18:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP3]](s1)
631  ; GFX10-NEXT:   [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY15]](s1), $exec_lo, implicit-def $scc
632  ; GFX10-NEXT:   [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY18]](s1), implicit-def $scc
633  ; GFX10-NEXT:   [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc
634  ; GFX10-NEXT: {{  $}}
635  ; GFX10-NEXT: bb.7:
636  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
637  ; GFX10-NEXT: {{  $}}
638  ; GFX10-NEXT:   [[PHI7:%[0-9]+]]:sreg_32(s1) = PHI [[COPY14]](s1), %bb.4, [[S_OR_B32_2]](s1), %bb.6
639  ; GFX10-NEXT:   [[PHI8:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.6, [[DEF]](s32), %bb.4
640  ; GFX10-NEXT:   [[COPY19:%[0-9]+]]:sreg_32(s1) = COPY [[PHI7]](s1)
641  ; GFX10-NEXT:   [[COPY20:%[0-9]+]]:sreg_32(s1) = COPY [[COPY19]](s1)
642  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF2]](s32)
643  ; GFX10-NEXT:   [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY12]](s1), $exec_lo, implicit-def $scc
644  ; GFX10-NEXT:   [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY20]](s1), implicit-def $scc
645  ; GFX10-NEXT:   [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc
646  ; GFX10-NEXT:   G_BR %bb.5
647  ; GFX10-NEXT: {{  $}}
648  ; GFX10-NEXT: bb.8:
649  ; GFX10-NEXT:   [[PHI9:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.3
650  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI9]](s32)
651  ; GFX10-NEXT:   S_ENDPGM 0
652  bb.0:
653    successors: %bb.1(0x80000000)
654    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
655
656    %0:_(s32) = COPY $vgpr0
657    %1:_(s32) = COPY $vgpr1
658    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
659    %3:_(s32) = COPY $vgpr2
660    %4:_(s32) = COPY $vgpr3
661    %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)
662    %6:_(s32) = COPY $vgpr4
663    %7:_(s32) = COPY $vgpr5
664    %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)
665    %9:_(s32) = COPY $vgpr6
666    %10:_(s32) = COPY $vgpr7
667    %11:_(p1) = G_MERGE_VALUES %9(s32), %10(s32)
668    %12:_(s32) = G_CONSTANT i32 0
669    %13:_(s32) = G_IMPLICIT_DEF
670
671  bb.1:
672    successors: %bb.2(0x40000000), %bb.3(0x40000000)
673
674    %14:_(s32) = G_PHI %15(s32), %bb.3, %12(s32), %bb.0
675    %16:_(s32) = G_PHI %12(s32), %bb.0, %17(s32), %bb.3
676    %18:_(s1) = G_CONSTANT i1 true
677    %19:_(s64) = G_SEXT %16(s32)
678    %20:_(s32) = G_CONSTANT i32 2
679    %21:_(s64) = G_SHL %19, %20(s32)
680    %22:_(p1) = G_PTR_ADD %5, %21(s64)
681    %23:_(s32) = G_LOAD %22(p1) :: (load (s32), addrspace 1)
682    %24:_(s32) = G_CONSTANT i32 0
683    %25:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %23(s32), %24
684    %26:sreg_32_xm0_xexec(s32) = SI_IF %25(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
685    G_BR %bb.2
686
687  bb.2:
688    successors: %bb.4(0x40000000), %bb.5(0x40000000)
689
690    %27:_(s1) = G_CONSTANT i1 true
691    %28:_(s32) = G_CONSTANT i32 2
692    %29:_(s64) = G_SHL %19, %28(s32)
693    %30:_(p1) = G_PTR_ADD %8, %29(s64)
694    %31:_(s32) = G_LOAD %30(p1) :: (load (s32), addrspace 1)
695    %32:_(s32) = G_CONSTANT i32 0
696    %33:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %31(s32), %32
697    %34:sreg_32_xm0_xexec(s32) = SI_IF %33(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
698    G_BR %bb.4
699
700  bb.3:
701    successors: %bb.8(0x04000000), %bb.1(0x7c000000)
702
703    %17:_(s32) = G_PHI %35(s32), %bb.5, %13(s32), %bb.1
704    %36:_(s1) = G_PHI %37(s1), %bb.5, %18(s1), %bb.1
705    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %26(s32)
706    %15:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %36(s1), %14(s32)
707    SI_LOOP %15(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
708    G_BR %bb.8
709
710  bb.4:
711    successors: %bb.6(0x40000000), %bb.7(0x40000000)
712
713    %38:_(s1) = G_CONSTANT i1 true
714    %39:_(s32) = G_CONSTANT i32 2
715    %40:_(s64) = G_SHL %19, %39(s32)
716    %41:_(p1) = G_PTR_ADD %11, %40(s64)
717    %42:_(s32) = G_LOAD %41(p1) :: (load (s32), addrspace 1)
718    %43:_(s32) = G_CONSTANT i32 0
719    %44:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %42(s32), %43
720    %45:sreg_32_xm0_xexec(s32) = SI_IF %44(s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
721    G_BR %bb.6
722
723  bb.5:
724    successors: %bb.3(0x80000000)
725
726    %35:_(s32) = G_PHI %46(s32), %bb.7, %13(s32), %bb.2
727    %37:_(s1) = G_PHI %47(s1), %bb.7, %27(s1), %bb.2
728    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32)
729    G_BR %bb.3
730
731  bb.6:
732    successors: %bb.7(0x80000000)
733
734    %48:_(s32) = G_CONSTANT i32 2
735    %49:_(s64) = G_SHL %19, %48(s32)
736    %50:_(p1) = G_PTR_ADD %2, %49(s64)
737    %51:_(s32) = G_LOAD %50(p1) :: (load (s32), addrspace 1)
738    %52:_(s32) = G_CONSTANT i32 1
739    %53:_(s32) = G_ADD %51, %52
740    G_STORE %53(s32), %50(p1) :: (store (s32), addrspace 1)
741    %54:_(s32) = G_ADD %16, %52
742    %55:_(s32) = G_CONSTANT i32 100
743    %56:_(s1) = G_ICMP intpred(ult), %16(s32), %55
744
745  bb.7:
746    successors: %bb.5(0x80000000)
747
748    %46:_(s32) = G_PHI %54(s32), %bb.6, %13(s32), %bb.4
749    %47:_(s1) = G_PHI %56(s1), %bb.6, %38(s1), %bb.4
750    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %45(s32)
751    G_BR %bb.5
752
753  bb.8:
754    %57:_(s32) = G_PHI %15(s32), %bb.3
755    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %57(s32)
756    S_ENDPGM 0
757...
758
759---
760name: loop_with_div_break_with_body
761legalized: true
762tracksRegLiveness: true
763body: |
764  ; GFX10-LABEL: name: loop_with_div_break_with_body
765  ; GFX10: bb.0:
766  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
767  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
768  ; GFX10-NEXT: {{  $}}
769  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
770  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
771  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
772  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
773  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
774  ; GFX10-NEXT:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
775  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
776  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
777  ; GFX10-NEXT:   [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
778  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
779  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
780  ; GFX10-NEXT:   [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
781  ; GFX10-NEXT:   [[DEF2:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
782  ; GFX10-NEXT:   [[DEF3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
783  ; GFX10-NEXT: {{  $}}
784  ; GFX10-NEXT: bb.1:
785  ; GFX10-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
786  ; GFX10-NEXT: {{  $}}
787  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[DEF3]](s1), %bb.0, %67(s1), %bb.5
788  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF2]](s1), %bb.0, %56(s1), %bb.5
789  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %43(s1), %bb.5
790  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.5, [[C]](s32), %bb.0
791  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.5
792  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI]](s1)
793  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
794  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI2]](s1)
795  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
796  ; GFX10-NEXT:   [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)
797  ; GFX10-NEXT:   [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)
798  ; GFX10-NEXT:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI4]](s32)
799  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
800  ; GFX10-NEXT:   [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
801  ; GFX10-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)
802  ; GFX10-NEXT:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
803  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
804  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
805  ; GFX10-NEXT:   [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc
806  ; GFX10-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY10]](s1), implicit-def $scc
807  ; GFX10-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
808  ; GFX10-NEXT:   [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
809  ; GFX10-NEXT:   [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY7]](s1), $exec_lo, implicit-def $scc
810  ; GFX10-NEXT:   [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc
811  ; GFX10-NEXT:   [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
812  ; GFX10-NEXT:   [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_1]](s1)
813  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
814  ; GFX10-NEXT:   G_BR %bb.3
815  ; GFX10-NEXT: {{  $}}
816  ; GFX10-NEXT: bb.2:
817  ; GFX10-NEXT:   successors: %bb.4(0x80000000)
818  ; GFX10-NEXT: {{  $}}
819  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
820  ; GFX10-NEXT:   G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1)
821  ; GFX10-NEXT:   G_BR %bb.4
822  ; GFX10-NEXT: {{  $}}
823  ; GFX10-NEXT: bb.3:
824  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
825  ; GFX10-NEXT: {{  $}}
826  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
827  ; GFX10-NEXT:   [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[C5]](s1)
828  ; GFX10-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
829  ; GFX10-NEXT:   [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C6]](s32)
830  ; GFX10-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64)
831  ; GFX10-NEXT:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)
832  ; GFX10-NEXT:   [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
833  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C7]]
834  ; GFX10-NEXT:   G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1)
835  ; GFX10-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI4]], [[C7]]
836  ; GFX10-NEXT:   [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
837  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI4]](s32), [[C8]]
838  ; GFX10-NEXT:   [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP1]](s1)
839  ; GFX10-NEXT:   [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY11]](s1), $exec_lo, implicit-def $scc
840  ; GFX10-NEXT:   [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY13]](s1), implicit-def $scc
841  ; GFX10-NEXT:   [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc
842  ; GFX10-NEXT:   [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY12]](s1), $exec_lo, implicit-def $scc
843  ; GFX10-NEXT:   [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY14]](s1), implicit-def $scc
844  ; GFX10-NEXT:   [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc
845  ; GFX10-NEXT:   G_BR %bb.5
846  ; GFX10-NEXT: {{  $}}
847  ; GFX10-NEXT: bb.4:
848  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32)
849  ; GFX10-NEXT:   S_ENDPGM 0
850  ; GFX10-NEXT: {{  $}}
851  ; GFX10-NEXT: bb.5:
852  ; GFX10-NEXT:   successors: %bb.6(0x04000000), %bb.1(0x7c000000)
853  ; GFX10-NEXT: {{  $}}
854  ; GFX10-NEXT:   [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_1]](s1), %bb.1, [[S_OR_B32_3]](s1), %bb.3
855  ; GFX10-NEXT:   [[PHI6:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, [[S_OR_B32_2]](s1), %bb.3
856  ; GFX10-NEXT:   [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.1
857  ; GFX10-NEXT:   [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)
858  ; GFX10-NEXT:   [[COPY16:%[0-9]+]]:sreg_32(s1) = COPY [[PHI6]](s1)
859  ; GFX10-NEXT:   [[COPY17:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[COPY16]](s1)
860  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
861  ; GFX10-NEXT:   [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY15]](s1), [[PHI3]](s32)
862  ; GFX10-NEXT:   [[S_ANDN2_B32_4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc
863  ; GFX10-NEXT:   [[S_AND_B32_4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY17]](s1), implicit-def $scc
864  ; GFX10-NEXT:   [[S_OR_B32_4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_4]](s1), [[S_AND_B32_4]](s1), implicit-def $scc
865  ; GFX10-NEXT:   SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
866  ; GFX10-NEXT:   G_BR %bb.6
867  ; GFX10-NEXT: {{  $}}
868  ; GFX10-NEXT: bb.6:
869  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
870  ; GFX10-NEXT: {{  $}}
871  ; GFX10-NEXT:   [[PHI8:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.5
872  ; GFX10-NEXT:   [[COPY18:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[S_OR_B32_4]](s1)
873  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI8]](s32)
874  ; GFX10-NEXT:   [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY18]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
875  ; GFX10-NEXT:   G_BR %bb.2
876  bb.0:
877    successors: %bb.1(0x80000000)
878    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
879
880    %0:_(s32) = COPY $vgpr0
881    %1:_(s32) = COPY $vgpr1
882    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
883    %3:_(s32) = COPY $vgpr2
884    %4:_(s32) = COPY $vgpr3
885    %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)
886    %6:_(s32) = COPY $vgpr4
887    %7:_(s32) = COPY $vgpr5
888    %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)
889    %9:_(s32) = G_CONSTANT i32 0
890    %10:_(s32) = G_IMPLICIT_DEF
891
892  bb.1:
893    successors: %bb.3(0x40000000), %bb.5(0x40000000)
894
895    %11:_(s32) = G_PHI %12(s32), %bb.5, %9(s32), %bb.0
896    %13:_(s32) = G_PHI %9(s32), %bb.0, %14(s32), %bb.5
897    %15:_(s1) = G_CONSTANT i1 true
898    %16:_(s64) = G_SEXT %13(s32)
899    %17:_(s32) = G_CONSTANT i32 2
900    %18:_(s64) = G_SHL %16, %17(s32)
901    %19:_(p1) = G_PTR_ADD %5, %18(s64)
902    %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1)
903    %21:_(s32) = G_CONSTANT i32 0
904    %22:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %20(s32), %21
905    %23:sreg_32_xm0_xexec(s32) = SI_IF %22(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
906    G_BR %bb.3
907
908  bb.2:
909    successors: %bb.4(0x80000000)
910
911    %24:_(s32) = G_CONSTANT i32 10
912    G_STORE %24(s32), %8(p1) :: (store (s32), addrspace 1)
913    G_BR %bb.4
914
915  bb.3:
916    successors: %bb.5(0x80000000)
917
918    %25:_(s1) = G_CONSTANT i1 false
919    %26:_(s32) = G_CONSTANT i32 2
920    %27:_(s64) = G_SHL %16, %26(s32)
921    %28:_(p1) = G_PTR_ADD %2, %27(s64)
922    %29:_(s32) = G_LOAD %28(p1) :: (load (s32), addrspace 1)
923    %30:_(s32) = G_CONSTANT i32 1
924    %31:_(s32) = G_ADD %29, %30
925    G_STORE %31(s32), %28(p1) :: (store (s32), addrspace 1)
926    %32:_(s32) = G_ADD %13, %30
927    %33:_(s32) = G_CONSTANT i32 100
928    %34:_(s1) = G_ICMP intpred(ult), %13(s32), %33
929    G_BR %bb.5
930
931  bb.4:
932    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32)
933    S_ENDPGM 0
934
935  bb.5:
936    successors: %bb.6(0x04000000), %bb.1(0x7c000000)
937
938    %14:_(s32) = G_PHI %32(s32), %bb.3, %10(s32), %bb.1
939    %36:_(s1) = G_PHI %25(s1), %bb.3, %15(s1), %bb.1
940    %37:_(s1) = G_PHI %34(s1), %bb.3, %15(s1), %bb.1
941    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32)
942    %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %37(s1), %11(s32)
943    SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
944    G_BR %bb.6
945
946  bb.6:
947    successors: %bb.2(0x40000000), %bb.4(0x40000000)
948
949    %38:sreg_32_xm0_xexec(s1) = G_PHI %36(s1), %bb.5
950    %39:_(s32) = G_PHI %12(s32), %bb.5
951    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %39(s32)
952    %35:sreg_32_xm0_xexec(s32) = SI_IF %38(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
953    G_BR %bb.2
954...
955
956---
957name: irreducible_cfg
958legalized: true
959tracksRegLiveness: true
960body: |
961  ; GFX10-LABEL: name: irreducible_cfg
962  ; GFX10: bb.0:
963  ; GFX10-NEXT:   successors: %bb.7(0x80000000)
964  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
965  ; GFX10-NEXT: {{  $}}
966  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
967  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
968  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
969  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
970  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
971  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
972  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
973  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
974  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY4]](s32), [[COPY1]]
975  ; GFX10-NEXT:   [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
976  ; GFX10-NEXT:   [[DEF2:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
977  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)
978  ; GFX10-NEXT:   G_BR %bb.7
979  ; GFX10-NEXT: {{  $}}
980  ; GFX10-NEXT: bb.1:
981  ; GFX10-NEXT:   successors: %bb.3(0x80000000)
982  ; GFX10-NEXT: {{  $}}
983  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
984  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY4]](s32), [[COPY]]
985  ; GFX10-NEXT:   G_BR %bb.3
986  ; GFX10-NEXT: {{  $}}
987  ; GFX10-NEXT: bb.2:
988  ; GFX10-NEXT:   successors: %bb.4(0x40000000), %bb.7(0x40000000)
989  ; GFX10-NEXT: {{  $}}
990  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI %53(s1), %bb.6, %57(s1), %bb.7
991  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI %35(s1), %bb.6, %34(s1), %bb.7
992  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s1) = G_PHI %12(s1), %bb.6, [[DEF]](s1), %bb.7
993  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI2]](s1)
994  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI]](s1)
995  ; GFX10-NEXT:   [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
996  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)
997  ; GFX10-NEXT:   [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY9]](s1), %17(s32)
998  ; GFX10-NEXT:   [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc
999  ; GFX10-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY7]](s1), implicit-def $scc
1000  ; GFX10-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
1001  ; GFX10-NEXT:   [[COPY10:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[S_OR_B32_]](s1)
1002  ; GFX10-NEXT:   SI_LOOP [[INT]](s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
1003  ; GFX10-NEXT:   G_BR %bb.4
1004  ; GFX10-NEXT: {{  $}}
1005  ; GFX10-NEXT: bb.3:
1006  ; GFX10-NEXT:   successors: %bb.6(0x04000000), %bb.3(0x7c000000)
1007  ; GFX10-NEXT: {{  $}}
1008  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1, %19(s32), %bb.3
1009  ; GFX10-NEXT:   [[INT1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ICMP1]](s1), [[PHI3]](s32)
1010  ; GFX10-NEXT:   SI_LOOP [[INT1]](s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
1011  ; GFX10-NEXT:   G_BR %bb.6
1012  ; GFX10-NEXT: {{  $}}
1013  ; GFX10-NEXT: bb.4:
1014  ; GFX10-NEXT:   successors: %bb.5(0x04000000), %bb.7(0x7c000000)
1015  ; GFX10-NEXT: {{  $}}
1016  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)
1017  ; GFX10-NEXT:   [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY5]](s32), [[COPY]]
1018  ; GFX10-NEXT:   [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)
1019  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
1020  ; GFX10-NEXT:   [[COPY12:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[C2]](s1)
1021  ; GFX10-NEXT:   [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C2]]
1022  ; GFX10-NEXT:   [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP2]], [[XOR]]
1023  ; GFX10-NEXT:   [[INT2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[OR]](s1), %25(s32)
1024  ; GFX10-NEXT:   [[DEF3:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
1025  ; GFX10-NEXT:   [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 %49(s1), $exec_lo, implicit-def $scc
1026  ; GFX10-NEXT:   [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc
1027  ; GFX10-NEXT:   [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
1028  ; GFX10-NEXT:   [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc
1029  ; GFX10-NEXT:   [[S_AND_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY12]](s1), implicit-def $scc
1030  ; GFX10-NEXT:   [[S_OR_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc
1031  ; GFX10-NEXT:   SI_LOOP [[INT2]](s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
1032  ; GFX10-NEXT:   G_BR %bb.5
1033  ; GFX10-NEXT: {{  $}}
1034  ; GFX10-NEXT: bb.5:
1035  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INT2]](s32), %bb.4
1036  ; GFX10-NEXT:   [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_1]](s1)
1037  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32)
1038  ; GFX10-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY13]](s1), [[COPY3]], [[COPY2]]
1039  ; GFX10-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[SELECT]](s32)
1040  ; GFX10-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)
1041  ; GFX10-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0
1042  ; GFX10-NEXT: {{  $}}
1043  ; GFX10-NEXT: bb.6:
1044  ; GFX10-NEXT:   successors: %bb.2(0x80000000)
1045  ; GFX10-NEXT: {{  $}}
1046  ; GFX10-NEXT:   [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[INT1]](s32), %bb.3
1047  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
1048  ; GFX10-NEXT:   [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)
1049  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI5]](s32)
1050  ; GFX10-NEXT:   [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 %42(s1), $exec_lo, implicit-def $scc
1051  ; GFX10-NEXT:   [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY14]](s1), implicit-def $scc
1052  ; GFX10-NEXT:   [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc
1053  ; GFX10-NEXT:   [[DEF4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
1054  ; GFX10-NEXT:   G_BR %bb.2
1055  ; GFX10-NEXT: {{  $}}
1056  ; GFX10-NEXT: bb.7:
1057  ; GFX10-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
1058  ; GFX10-NEXT: {{  $}}
1059  ; GFX10-NEXT:   [[PHI6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[COPY6]](s1), %bb.0, [[S_OR_B32_]](s1), %bb.2, [[S_OR_B32_2]](s1), %bb.4
1060  ; GFX10-NEXT:   [[PHI7:%[0-9]+]]:sreg_32(s1) = PHI [[DEF2]](s1), %bb.0, [[PHI7]](s1), %bb.2, [[S_OR_B32_1]](s1), %bb.4
1061  ; GFX10-NEXT:   [[PHI8:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, [[PHI1]](s1), %bb.2, [[DEF3]](s1), %bb.4
1062  ; GFX10-NEXT:   [[PHI9:%[0-9]+]]:_(s32) = G_PHI [[INT2]](s32), %bb.4, [[PHI9]](s32), %bb.2, [[C]](s32), %bb.0
1063  ; GFX10-NEXT:   [[PHI10:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.4, [[INT]](s32), %bb.2, [[C]](s32), %bb.0
1064  ; GFX10-NEXT:   [[COPY15:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI6]](s1)
1065  ; GFX10-NEXT:   [[COPY16:%[0-9]+]]:sreg_32(s1) = COPY [[PHI7]](s1)
1066  ; GFX10-NEXT:   [[COPY17:%[0-9]+]]:sreg_32(s1) = COPY [[PHI8]](s1)
1067  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
1068  ; GFX10-NEXT:   [[COPY18:%[0-9]+]]:sreg_32(s1) = COPY [[C4]](s1)
1069  ; GFX10-NEXT:   [[S_ANDN2_B32_4:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY17]](s1), $exec_lo, implicit-def $scc
1070  ; GFX10-NEXT:   [[S_AND_B32_4:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY18]](s1), implicit-def $scc
1071  ; GFX10-NEXT:   [[S_OR_B32_4:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_4]](s1), [[S_AND_B32_4]](s1), implicit-def $scc
1072  ; GFX10-NEXT:   [[COPY19:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_4]](s1)
1073  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY15]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
1074  ; GFX10-NEXT:   G_BR %bb.1
1075  bb.0:
1076    successors: %bb.7(0x80000000)
1077    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
1078
1079    %0:_(s32) = COPY $vgpr0
1080    %1:_(s32) = COPY $vgpr1
1081    %2:_(s32) = COPY $vgpr2
1082    %3:_(s32) = COPY $vgpr3
1083    %4:_(s32) = COPY $vgpr4
1084    %5:_(s32) = COPY $vgpr5
1085    %6:_(s32) = G_CONSTANT i32 0
1086    %7:_(s1) = G_IMPLICIT_DEF
1087    %8:_(s1) = G_ICMP intpred(sgt), %4(s32), %1
1088    G_BR %bb.7
1089
1090  bb.1:
1091    successors: %bb.3(0x80000000)
1092
1093    %9:_(s32) = G_CONSTANT i32 0
1094    %10:_(s1) = G_ICMP intpred(sle), %4(s32), %0
1095    G_BR %bb.3
1096
1097  bb.2:
1098    successors: %bb.4(0x40000000), %bb.7(0x40000000)
1099
1100    %11:_(s1) = G_PHI %12(s1), %bb.6, %7(s1), %bb.7
1101    %13:_(s1) = G_PHI %12(s1), %bb.6, %14(s1), %bb.7
1102    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)
1103    %16:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %13(s1), %17(s32)
1104    SI_LOOP %16(s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
1105    G_BR %bb.4
1106
1107  bb.3:
1108    successors: %bb.6(0x04000000), %bb.3(0x7c000000)
1109
1110    %18:_(s32) = G_PHI %9(s32), %bb.1, %19(s32), %bb.3
1111    %19:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %10(s1), %18(s32)
1112    SI_LOOP %19(s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
1113    G_BR %bb.6
1114
1115  bb.4:
1116    successors: %bb.5(0x04000000), %bb.7(0x7c000000)
1117
1118    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %16(s32)
1119    %20:_(s1) = G_ICMP intpred(sgt), %5(s32), %0
1120    %21:_(s1) = G_CONSTANT i1 true
1121    %22:_(s1) = G_XOR %8, %21
1122    %23:_(s1) = G_OR %20, %22
1123    %24:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %23(s1), %25(s32)
1124    SI_LOOP %24(s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
1125    G_BR %bb.5
1126
1127  bb.5:
1128    %26:_(s1) = G_PHI %20(s1), %bb.4
1129    %27:_(s32) = G_PHI %24(s32), %bb.4
1130    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %27(s32)
1131    %28:_(s32) = G_SELECT %26(s1), %3, %2
1132    %29:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %28(s32)
1133    $sgpr0 = COPY %29(s32)
1134    SI_RETURN_TO_EPILOG implicit $sgpr0
1135
1136  bb.6:
1137    successors: %bb.2(0x80000000)
1138
1139    %30:_(s32) = G_PHI %19(s32), %bb.3
1140    %12:_(s1) = G_CONSTANT i1 false
1141    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %30(s32)
1142    G_BR %bb.2
1143
1144  bb.7:
1145    successors: %bb.1(0x40000000), %bb.2(0x40000000)
1146
1147    %25:_(s32) = G_PHI %24(s32), %bb.4, %25(s32), %bb.2, %6(s32), %bb.0
1148    %17:_(s32) = G_PHI %6(s32), %bb.4, %16(s32), %bb.2, %6(s32), %bb.0
1149    %31:sreg_32_xm0_xexec(s1) = G_PHI %8(s1), %bb.0, %11(s1), %bb.2, %21(s1), %bb.4
1150    %14:_(s1) = G_CONSTANT i1 true
1151    %15:sreg_32_xm0_xexec(s32) = SI_IF %31(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
1152    G_BR %bb.1
1153...
1154