1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s 3 4--- 5name: known_sign_bits_smed3_0 6legalized: true 7tracksRegLiveness: true 8body: | 9 bb.0: 10 liveins: $vgpr0 11 12 ; CHECK-LABEL: name: known_sign_bits_smed3_0 13 ; CHECK: liveins: $vgpr0 14 ; CHECK-NEXT: {{ $}} 15 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0 16 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8 17 ; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -255 18 ; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 255 19 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2 20 ; CHECK-NEXT: $vgpr0 = COPY %smed3(s32) 21 %val:_(s32) = COPY $vgpr0 22 %val0:_(s32) = G_SEXT_INREG %val, 8 23 %val1:_(s32) = G_CONSTANT i32 -255 24 %val2:_(s32) = G_CONSTANT i32 255 25 %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2 26 %inreg:_(s32) = G_SEXT_INREG %smed3, 9 27 $vgpr0 = COPY %inreg 28 29... 30 31--- 32name: known_sign_bits_smed3_1 33legalized: true 34tracksRegLiveness: true 35body: | 36 bb.0: 37 liveins: $vgpr0 38 39 ; CHECK-LABEL: name: known_sign_bits_smed3_1 40 ; CHECK: liveins: $vgpr0 41 ; CHECK-NEXT: {{ $}} 42 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0 43 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8 44 ; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -255 45 ; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 255 46 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val0, %val2 47 ; CHECK-NEXT: $vgpr0 = COPY %smed3(s32) 48 %val:_(s32) = COPY $vgpr0 49 %val0:_(s32) = G_SEXT_INREG %val, 8 50 %val1:_(s32) = G_CONSTANT i32 -255 51 %val2:_(s32) = G_CONSTANT i32 255 52 %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val0, %val2 53 %inreg:_(s32) = G_SEXT_INREG %smed3, 9 54 $vgpr0 = COPY %inreg 55 56... 57 58--- 59name: known_sign_bits_smed3_2 60legalized: true 61tracksRegLiveness: true 62body: | 63 bb.0: 64 liveins: $vgpr0 65 66 ; CHECK-LABEL: name: known_sign_bits_smed3_2 67 ; CHECK: liveins: $vgpr0 68 ; CHECK-NEXT: {{ $}} 69 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0 70 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8 71 ; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -256 72 ; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 128 73 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val2, %val0 74 ; CHECK-NEXT: $vgpr0 = COPY %smed3(s32) 75 %val:_(s32) = COPY $vgpr0 76 %val0:_(s32) = G_SEXT_INREG %val, 8 77 %val1:_(s32) = G_CONSTANT i32 -256 78 %val2:_(s32) = G_CONSTANT i32 128 79 %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val2, %val0 80 %inreg:_(s32) = G_SEXT_INREG %smed3, 9 81 $vgpr0 = COPY %inreg 82 83... 84 85--- 86name: not_enough_sign_bits_smed3_0 87legalized: true 88tracksRegLiveness: true 89body: | 90 bb.0: 91 liveins: $vgpr0, $vgpr1, $vgpr2 92 93 ; CHECK-LABEL: name: not_enough_sign_bits_smed3_0 94 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 95 ; CHECK-NEXT: {{ $}} 96 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0 97 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8 98 ; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 9 99 ; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9 100 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2 101 ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8 102 ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32) 103 %val:_(s32) = COPY $vgpr0 104 %val0:_(s32) = G_SEXT_INREG %val, 8 105 %val1:_(s32) = G_SEXT_INREG %val, 9 106 %val2:_(s32) = G_SEXT_INREG %val, 9 107 %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2 108 %inreg:_(s32) = G_SEXT_INREG %smed3, 8 109 $vgpr0 = COPY %inreg 110 111... 112 113--- 114name: not_enough_sign_bits_smed3_1 115legalized: true 116tracksRegLiveness: true 117body: | 118 bb.0: 119 liveins: $vgpr0, $vgpr1, $vgpr2 120 121 ; CHECK-LABEL: name: not_enough_sign_bits_smed3_1 122 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 123 ; CHECK-NEXT: {{ $}} 124 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0 125 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 9 126 ; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 8 127 ; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9 128 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2 129 ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8 130 ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32) 131 %val:_(s32) = COPY $vgpr0 132 %val0:_(s32) = G_SEXT_INREG %val, 9 133 %val1:_(s32) = G_SEXT_INREG %val, 8 134 %val2:_(s32) = G_SEXT_INREG %val, 9 135 %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2 136 %inreg:_(s32) = G_SEXT_INREG %smed3, 8 137 $vgpr0 = COPY %inreg 138 139... 140 141--- 142name: not_enough_sign_bits_smed3_2 143legalized: true 144tracksRegLiveness: true 145body: | 146 bb.0: 147 liveins: $vgpr0, $vgpr1, $vgpr2 148 149 ; CHECK-LABEL: name: not_enough_sign_bits_smed3_2 150 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 151 ; CHECK-NEXT: {{ $}} 152 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0 153 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8 154 ; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 8 155 ; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9 156 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2 157 ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8 158 ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32) 159 %val:_(s32) = COPY $vgpr0 160 %val0:_(s32) = G_SEXT_INREG %val, 8 161 %val1:_(s32) = G_SEXT_INREG %val, 8 162 %val2:_(s32) = G_SEXT_INREG %val, 9 163 %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2 164 %inreg:_(s32) = G_SEXT_INREG %smed3, 8 165 $vgpr0 = COPY %inreg 166 167... 168