xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name: rotl_i32
6tracksRegLiveness: true
7body: |
8  bb.0:
9    liveins: $vgpr0, $vgpr1, $vgpr2
10
11    ; CHECK-LABEL: name: rotl_i32
12    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
13    ; CHECK-NEXT: {{  $}}
14    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
15    ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
16    ; CHECK-NEXT: %or:_(s32) = G_ROTL %a, %amt(s32)
17    ; CHECK-NEXT: $vgpr2 = COPY %or(s32)
18    %a:_(s32) = COPY $vgpr0
19    %amt:_(s32) = COPY $vgpr1
20    %bw:_(s32) = G_CONSTANT i32 32
21    %shl:_(s32) = G_SHL %a, %amt
22    %sub:_(s32) = G_SUB %bw, %amt
23    %lshr:_(s32) = G_LSHR %a, %sub
24    %or:_(s32) = G_OR %shl, %lshr
25    $vgpr2 = COPY %or
26...
27
28---
29name: rotl_v2i32
30tracksRegLiveness: true
31body: |
32  bb.0:
33    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
34
35    ; CHECK-LABEL: name: rotl_v2i32
36    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
37    ; CHECK-NEXT: {{  $}}
38    ; CHECK-NEXT: %a:_(<2 x s32>) = COPY $vgpr0_vgpr1
39    ; CHECK-NEXT: %amt:_(<2 x s32>) = COPY $vgpr2_vgpr3
40    ; CHECK-NEXT: %or:_(<2 x s32>) = G_ROTL %a, %amt(<2 x s32>)
41    ; CHECK-NEXT: $vgpr4_vgpr5 = COPY %or(<2 x s32>)
42    %a:_(<2 x s32>) = COPY $vgpr0_vgpr1
43    %amt:_(<2 x s32>) = COPY $vgpr2_vgpr3
44    %scalar_bw:_(s32) = G_CONSTANT i32 32
45    %bw:_(<2 x s32>) = G_BUILD_VECTOR %scalar_bw, %scalar_bw
46    %shl:_(<2 x s32>) = G_SHL %a, %amt
47    %sub:_(<2 x s32>) = G_SUB %bw, %amt
48    %lshr:_(<2 x s32>) = G_LSHR %a, %sub
49    %or:_(<2 x s32>) = G_OR %shl, %lshr
50    $vgpr4_vgpr5 = COPY %or
51...
52
53---
54name: rotl_commute_i32
55tracksRegLiveness: true
56body: |
57  bb.0:
58    liveins: $vgpr0, $vgpr1, $vgpr2
59
60    ; CHECK-LABEL: name: rotl_commute_i32
61    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
62    ; CHECK-NEXT: {{  $}}
63    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
64    ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
65    ; CHECK-NEXT: %or:_(s32) = G_ROTL %a, %amt(s32)
66    ; CHECK-NEXT: $vgpr2 = COPY %or(s32)
67    %a:_(s32) = COPY $vgpr0
68    %amt:_(s32) = COPY $vgpr1
69    %bw:_(s32) = G_CONSTANT i32 32
70    %shl:_(s32) = G_SHL %a, %amt
71    %sub:_(s32) = G_SUB %bw, %amt
72    %lshr:_(s32) = G_LSHR %a, %sub
73    %or:_(s32) = G_OR %lshr, %shl
74    $vgpr2 = COPY %or
75...
76
77---
78name: rotr_i32
79tracksRegLiveness: true
80body: |
81  bb.0:
82    liveins: $vgpr0, $vgpr1, $vgpr2
83
84    ; CHECK-LABEL: name: rotr_i32
85    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
86    ; CHECK-NEXT: {{  $}}
87    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
88    ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
89    ; CHECK-NEXT: %or:_(s32) = G_ROTR %a, %amt(s32)
90    ; CHECK-NEXT: $vgpr2 = COPY %or(s32)
91    %a:_(s32) = COPY $vgpr0
92    %amt:_(s32) = COPY $vgpr1
93    %bw:_(s32) = G_CONSTANT i32 32
94    %lshr:_(s32) = G_LSHR %a, %amt
95    %sub:_(s32) = G_SUB %bw, %amt
96    %shl:_(s32) = G_SHL %a, %sub
97    %or:_(s32) = G_OR %shl, %lshr
98    $vgpr2 = COPY %or
99...
100
101---
102name: rot_i32_const
103tracksRegLiveness: true
104body: |
105  bb.0:
106    liveins: $vgpr0, $vgpr1
107
108    ; CHECK-LABEL: name: rot_i32_const
109    ; CHECK: liveins: $vgpr0, $vgpr1
110    ; CHECK-NEXT: {{  $}}
111    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
112    ; CHECK-NEXT: %amt1:_(s32) = G_CONSTANT i32 12
113    ; CHECK-NEXT: %or:_(s32) = G_ROTR %a, %amt1(s32)
114    ; CHECK-NEXT: $vgpr1 = COPY %or(s32)
115    %a:_(s32) = COPY $vgpr0
116    %amt0:_(s32) = G_CONSTANT i32 20
117    %amt1:_(s32) = G_CONSTANT i32 12
118    %shl:_(s32) = G_SHL %a, %amt0
119    %lshr:_(s32) = G_LSHR %a, %amt1
120    %or:_(s32) = G_OR %shl, %lshr
121    $vgpr1 = COPY %or
122...
123
124---
125name: rot_v2i32_const
126tracksRegLiveness: true
127body: |
128  bb.0:
129    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
130
131    ; CHECK-LABEL: name: rot_v2i32_const
132    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
133    ; CHECK-NEXT: {{  $}}
134    ; CHECK-NEXT: %a:_(<2 x s32>) = COPY $vgpr0_vgpr1
135    ; CHECK-NEXT: %scalar_amt1:_(s32) = G_CONSTANT i32 12
136    ; CHECK-NEXT: %amt1:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt1(s32), %scalar_amt1(s32)
137    ; CHECK-NEXT: %or:_(<2 x s32>) = G_ROTR %a, %amt1(<2 x s32>)
138    ; CHECK-NEXT: $vgpr2_vgpr3 = COPY %or(<2 x s32>)
139    %a:_(<2 x s32>) = COPY $vgpr0_vgpr1
140    %scalar_amt0:_(s32) = G_CONSTANT i32 20
141    %amt0:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt0, %scalar_amt0
142    %scalar_amt1:_(s32) = G_CONSTANT i32 12
143    %amt1:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt1, %scalar_amt1
144    %shl:_(<2 x s32>) = G_SHL %a, %amt0
145    %lshr:_(<2 x s32>) = G_LSHR %a, %amt1
146    %or:_(<2 x s32>) = G_OR %shl, %lshr
147    $vgpr2_vgpr3 = COPY %or
148...
149
150---
151name: rot_i32_bad_const
152tracksRegLiveness: true
153body: |
154  bb.0:
155    liveins: $vgpr0, $vgpr1
156
157    ; CHECK-LABEL: name: rot_i32_bad_const
158    ; CHECK: liveins: $vgpr0, $vgpr1
159    ; CHECK-NEXT: {{  $}}
160    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
161    ; CHECK-NEXT: %amt0:_(s32) = G_CONSTANT i32 20
162    ; CHECK-NEXT: %amt1:_(s32) = G_CONSTANT i32 11
163    ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt0(s32)
164    ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %amt1(s32)
165    ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
166    ; CHECK-NEXT: $vgpr1 = COPY %or(s32)
167    %a:_(s32) = COPY $vgpr0
168    %amt0:_(s32) = G_CONSTANT i32 20
169    %amt1:_(s32) = G_CONSTANT i32 11
170    %shl:_(s32) = G_SHL %a, %amt0
171    %lshr:_(s32) = G_LSHR %a, %amt1
172    %or:_(s32) = G_OR %shl, %lshr
173    $vgpr1 = COPY %or
174...
175
176
177---
178name: rotl_i32_bad_bw
179tracksRegLiveness: true
180body: |
181  bb.0:
182    liveins: $vgpr0, $vgpr1, $vgpr2
183
184    ; CHECK-LABEL: name: rotl_i32_bad_bw
185    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
186    ; CHECK-NEXT: {{  $}}
187    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
188    ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
189    ; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 31
190    ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
191    ; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt
192    ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %sub(s32)
193    ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
194    ; CHECK-NEXT: $vgpr2 = COPY %or(s32)
195    %a:_(s32) = COPY $vgpr0
196    %amt:_(s32) = COPY $vgpr1
197    %bw:_(s32) = G_CONSTANT i32 31
198    %shl:_(s32) = G_SHL %a, %amt
199    %sub:_(s32) = G_SUB %bw, %amt
200    %lshr:_(s32) = G_LSHR %a, %sub
201    %or:_(s32) = G_OR %shl, %lshr
202    $vgpr2 = COPY %or
203...
204
205---
206name: rotl_i32_bad_amt_reg
207tracksRegLiveness: true
208body: |
209  bb.0:
210    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
211
212    ; CHECK-LABEL: name: rotl_i32_bad_amt_reg
213    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
214    ; CHECK-NEXT: {{  $}}
215    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
216    ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
217    ; CHECK-NEXT: %amt1:_(s32) = COPY $vgpr2
218    ; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 32
219    ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
220    ; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt1
221    ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %sub(s32)
222    ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
223    ; CHECK-NEXT: $vgpr3 = COPY %or(s32)
224    %a:_(s32) = COPY $vgpr0
225    %amt:_(s32) = COPY $vgpr1
226    %amt1:_(s32) = COPY $vgpr2
227    %bw:_(s32) = G_CONSTANT i32 32
228    %shl:_(s32) = G_SHL %a, %amt
229    %sub:_(s32) = G_SUB %bw, %amt1
230    %lshr:_(s32) = G_LSHR %a, %sub
231    %or:_(s32) = G_OR %shl, %lshr
232    $vgpr3 = COPY %or
233...
234