xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK
3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK
4
5---
6name:            test_fminnum
7body:             |
8  bb.0:
9    liveins: $vgpr0, $vgpr1
10
11    ; CHECK-LABEL: name: test_fminnum
12    ; CHECK: liveins: $vgpr0, $vgpr1
13    ; CHECK-NEXT: {{  $}}
14    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
15    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
16    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
17    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
18    ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[FNEG]], [[FNEG1]]
19    ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
20    %0:_(s32) = COPY $vgpr0
21    %1:_(s32) = COPY $vgpr1
22    %2:_(s32) = G_FMINNUM %0, %1
23    %3:_(s32) = G_FNEG %2
24    $vgpr0 = COPY %3(s32)
25
26...
27---
28name:            test_fmaxnum
29body:             |
30  bb.0:
31    liveins: $vgpr0, $vgpr1
32
33    ; CHECK-LABEL: name: test_fmaxnum
34    ; CHECK: liveins: $vgpr0, $vgpr1
35    ; CHECK-NEXT: {{  $}}
36    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
37    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
38    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
39    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
40    ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[FNEG]], [[FNEG1]]
41    ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
42    %0:_(s32) = COPY $vgpr0
43    %1:_(s32) = COPY $vgpr1
44    %2:_(s32) = G_FMAXNUM %0, %1
45    %3:_(s32) = G_FNEG %2
46    $vgpr0 = COPY %3(s32)
47
48...
49---
50name:            test_fminnum_ieee
51body:             |
52  bb.0:
53    liveins: $vgpr0, $vgpr1
54
55    ; CHECK-LABEL: name: test_fminnum_ieee
56    ; CHECK: liveins: $vgpr0, $vgpr1
57    ; CHECK-NEXT: {{  $}}
58    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
59    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
60    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
61    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
62    ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FNEG]], [[FNEG1]]
63    ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
64    %0:_(s32) = COPY $vgpr0
65    %1:_(s32) = COPY $vgpr1
66    %2:_(s32) = G_FMINNUM_IEEE %0, %1
67    %3:_(s32) = G_FNEG %2
68    $vgpr0 = COPY %3(s32)
69
70...
71---
72name:            test_fmaxnum_ieee
73body:             |
74  bb.0:
75    liveins: $vgpr0, $vgpr1
76
77    ; CHECK-LABEL: name: test_fmaxnum_ieee
78    ; CHECK: liveins: $vgpr0, $vgpr1
79    ; CHECK-NEXT: {{  $}}
80    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
81    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
82    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
83    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
84    ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FNEG]], [[FNEG1]]
85    ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
86    %0:_(s32) = COPY $vgpr0
87    %1:_(s32) = COPY $vgpr1
88    %2:_(s32) = G_FMAXNUM_IEEE %0, %1
89    %3:_(s32) = G_FNEG %2
90    $vgpr0 = COPY %3(s32)
91
92...
93---
94name:            test_amdgpu_fmin_legacy
95body:             |
96  bb.0:
97    liveins: $vgpr0, $vgpr1
98
99    ; CHECK-LABEL: name: test_amdgpu_fmin_legacy
100    ; CHECK: liveins: $vgpr0, $vgpr1
101    ; CHECK-NEXT: {{  $}}
102    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
103    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
104    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
105    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
106    ; CHECK-NEXT: [[AMDGPU_FMAX_LEGACY:%[0-9]+]]:_(s32) = G_AMDGPU_FMAX_LEGACY [[FNEG]], [[FNEG1]]
107    ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMAX_LEGACY]](s32)
108    %0:_(s32) = COPY $vgpr0
109    %1:_(s32) = COPY $vgpr1
110    %2:_(s32) = G_AMDGPU_FMIN_LEGACY %0, %1
111    %3:_(s32) = G_FNEG %2
112    $vgpr0 = COPY %3(s32)
113
114...
115---
116name:            test_amdgpu_fmax_legacy
117body:             |
118  bb.0:
119    liveins: $vgpr0, $vgpr1
120
121    ; CHECK-LABEL: name: test_amdgpu_fmax_legacy
122    ; CHECK: liveins: $vgpr0, $vgpr1
123    ; CHECK-NEXT: {{  $}}
124    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
125    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
126    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
127    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
128    ; CHECK-NEXT: [[AMDGPU_FMIN_LEGACY:%[0-9]+]]:_(s32) = G_AMDGPU_FMIN_LEGACY [[FNEG]], [[FNEG1]]
129    ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMIN_LEGACY]](s32)
130    %0:_(s32) = COPY $vgpr0
131    %1:_(s32) = COPY $vgpr1
132    %2:_(s32) = G_AMDGPU_FMAX_LEGACY %0, %1
133    %3:_(s32) = G_FNEG %2
134    $vgpr0 = COPY %3(s32)
135
136...
137---
138name:            test_fadd
139body:             |
140  bb.0:
141    liveins: $vgpr0, $vgpr1
142
143    ; CHECK-LABEL: name: test_fadd
144    ; CHECK: liveins: $vgpr0, $vgpr1
145    ; CHECK-NEXT: {{  $}}
146    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
147    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
148    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
149    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[FNEG]], [[COPY1]]
150    ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
151    %0:_(s32) = COPY $vgpr0
152    %1:_(s32) = COPY $vgpr1
153    %2:_(s32) = nsz G_FADD %0, %1
154    %3:_(s32) = G_FNEG %2
155    $vgpr0 = COPY %3(s32)
156
157...
158---
159name:            test_fsub
160body:             |
161  bb.0:
162    liveins: $vgpr0, $vgpr1
163
164    ; CHECK-LABEL: name: test_fsub
165    ; CHECK: liveins: $vgpr0, $vgpr1
166    ; CHECK-NEXT: {{  $}}
167    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
168    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
169    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[COPY1]], [[COPY]]
170    ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
171    %0:_(s32) = COPY $vgpr0
172    %1:_(s32) = COPY $vgpr1
173    %2:_(s32) = nsz G_FSUB %0, %1
174    %3:_(s32) = G_FNEG %2
175    $vgpr0 = COPY %3(s32)
176
177...
178---
179name:            test_fma
180body:             |
181  bb.0:
182    liveins: $vgpr0, $vgpr1, $vgpr2
183
184    ; CHECK-LABEL: name: test_fma
185    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
186    ; CHECK-NEXT: {{  $}}
187    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
188    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
189    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
190    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
191    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]]
192    ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = nsz G_FMA [[COPY]], [[FNEG]], [[FNEG1]]
193    ; CHECK-NEXT: $vgpr0 = COPY [[FMA]](s32)
194    %0:_(s32) = COPY $vgpr0
195    %1:_(s32) = COPY $vgpr1
196    %2:_(s32) = COPY $vgpr2
197    %3:_(s32) = nsz G_FMA %0, %1, %2
198    %4:_(s32) = G_FNEG %3
199    $vgpr0 = COPY %4(s32)
200
201...
202---
203name:            test_fmad
204body:             |
205  bb.0:
206    liveins: $vgpr0, $vgpr1, $vgpr2
207
208    ; CHECK-LABEL: name: test_fmad
209    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
210    ; CHECK-NEXT: {{  $}}
211    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
212    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
213    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
214    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
215    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]]
216    ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = nsz G_FMAD [[COPY]], [[FNEG]], [[FNEG1]]
217    ; CHECK-NEXT: $vgpr0 = COPY [[FMAD]](s32)
218    %0:_(s32) = COPY $vgpr0
219    %1:_(s32) = COPY $vgpr1
220    %2:_(s32) = COPY $vgpr2
221    %3:_(s32) = nsz G_FMAD %0, %1, %2
222    %4:_(s32) = G_FNEG %3
223    $vgpr0 = COPY %4(s32)
224
225...
226---
227name:            test_fmul
228body:             |
229  bb.0:
230    liveins: $vgpr0, $vgpr1
231
232    ; CHECK-LABEL: name: test_fmul
233    ; CHECK: liveins: $vgpr0, $vgpr1
234    ; CHECK-NEXT: {{  $}}
235    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
236    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
237    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
238    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[FNEG]]
239    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)
240    %0:_(s32) = COPY $vgpr0
241    %1:_(s32) = COPY $vgpr1
242    %2:_(s32) = G_FMUL %0, %1
243    %3:_(s32) = G_FNEG %2
244    $vgpr0 = COPY %3(s32)
245
246...
247---
248name:            test_fpext
249body:             |
250  bb.0:
251    liveins: $vgpr0
252
253    ; CHECK-LABEL: name: test_fpext
254    ; CHECK: liveins: $vgpr0
255    ; CHECK-NEXT: {{  $}}
256    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
257    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
258    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC]]
259    ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)
260    ; CHECK-NEXT: $vgpr0 = COPY [[FPEXT]](s32)
261    %0:_(s32) = COPY $vgpr0
262    %1:_(s16) = G_TRUNC %0(s32)
263    %2:_(s32) = G_FPEXT %1(s16)
264    %3:_(s32) = G_FNEG %2
265    $vgpr0 = COPY %3(s32)
266
267...
268---
269name:            test_intrinsic_trunc
270body:             |
271  bb.0:
272    liveins: $vgpr0
273
274    ; CHECK-LABEL: name: test_intrinsic_trunc
275    ; CHECK: liveins: $vgpr0
276    ; CHECK-NEXT: {{  $}}
277    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
278    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
279    ; CHECK-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FNEG]]
280    ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32)
281    %0:_(s32) = COPY $vgpr0
282    %1:_(s32) = G_INTRINSIC_TRUNC %0
283    %2:_(s32) = G_FNEG %1
284    $vgpr0 = COPY %2(s32)
285
286...
287---
288name:            test_frint
289body:             |
290  bb.0:
291    liveins: $vgpr0
292
293    ; CHECK-LABEL: name: test_frint
294    ; CHECK: liveins: $vgpr0
295    ; CHECK-NEXT: {{  $}}
296    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
297    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
298    ; CHECK-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FNEG]]
299    ; CHECK-NEXT: $vgpr0 = COPY [[FRINT]](s32)
300    %0:_(s32) = COPY $vgpr0
301    %1:_(s32) = G_FRINT %0
302    %2:_(s32) = G_FNEG %1
303    $vgpr0 = COPY %2(s32)
304
305...
306---
307name:            test_fnearbyint
308body:             |
309  bb.0:
310    liveins: $vgpr0
311
312    ; CHECK-LABEL: name: test_fnearbyint
313    ; CHECK: liveins: $vgpr0
314    ; CHECK-NEXT: {{  $}}
315    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
316    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
317    ; CHECK-NEXT: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FNEG]]
318    ; CHECK-NEXT: $vgpr0 = COPY [[FNEARBYINT]](s32)
319    %0:_(s32) = COPY $vgpr0
320    %1:_(s32) = G_FNEARBYINT %0
321    %2:_(s32) = G_FNEG %1
322    $vgpr0 = COPY %2(s32)
323
324...
325---
326name:            test_intrinsic_round
327body:             |
328  bb.0:
329    liveins: $vgpr0
330
331    ; CHECK-LABEL: name: test_intrinsic_round
332    ; CHECK: liveins: $vgpr0
333    ; CHECK-NEXT: {{  $}}
334    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
335    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
336    ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FNEG]]
337    ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_ROUND]](s32)
338    %0:_(s32) = COPY $vgpr0
339    %1:_(s32) = G_INTRINSIC_ROUND %0
340    %2:_(s32) = G_FNEG %1
341    $vgpr0 = COPY %2(s32)
342
343...
344---
345name:            test_intrinsic_roundeven
346body:             |
347  bb.0:
348    liveins: $vgpr0
349
350    ; CHECK-LABEL: name: test_intrinsic_roundeven
351    ; CHECK: liveins: $vgpr0
352    ; CHECK-NEXT: {{  $}}
353    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
354    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
355    ; CHECK-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FNEG]]
356    ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_ROUNDEVEN]](s32)
357    %0:_(s32) = COPY $vgpr0
358    %1:_(s32) = G_INTRINSIC_ROUNDEVEN %0
359    %2:_(s32) = G_FNEG %1
360    $vgpr0 = COPY %2(s32)
361
362...
363---
364name:            test_fsin
365body:             |
366  bb.0:
367    liveins: $vgpr0
368
369    ; CHECK-LABEL: name: test_fsin
370    ; CHECK: liveins: $vgpr0
371    ; CHECK-NEXT: {{  $}}
372    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
373    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
374    ; CHECK-NEXT: [[FSIN:%[0-9]+]]:_(s32) = G_FSIN [[FNEG]]
375    ; CHECK-NEXT: $vgpr0 = COPY [[FSIN]](s32)
376    %0:_(s32) = COPY $vgpr0
377    %1:_(s32) = G_FSIN %0
378    %2:_(s32) = G_FNEG %1
379    $vgpr0 = COPY %2(s32)
380
381...
382---
383name:            test_fcanonicalize
384body:             |
385  bb.0:
386    liveins: $vgpr0
387
388    ; CHECK-LABEL: name: test_fcanonicalize
389    ; CHECK: liveins: $vgpr0
390    ; CHECK-NEXT: {{  $}}
391    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
392    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
393    ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[FNEG]]
394    ; CHECK-NEXT: $vgpr0 = COPY [[FCANONICALIZE]](s32)
395    %0:_(s32) = COPY $vgpr0
396    %1:_(s32) = G_FCANONICALIZE %0
397    %2:_(s32) = G_FNEG %1
398    $vgpr0 = COPY %2(s32)
399
400...
401---
402name:            test_amdgcn_rcp_iflag
403body:             |
404  bb.0:
405    liveins: $vgpr0
406
407    ; CHECK-LABEL: name: test_amdgcn_rcp_iflag
408    ; CHECK: liveins: $vgpr0
409    ; CHECK-NEXT: {{  $}}
410    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
411    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
412    ; CHECK-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FNEG]](s32)
413    ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_RCP_IFLAG]](s32)
414    %0:_(s32) = COPY $vgpr0
415    %1:_(s32) = G_AMDGPU_RCP_IFLAG %0
416    %2:_(s32) = G_FNEG %1
417    $vgpr0 = COPY %2(s32)
418
419...
420---
421name:            test_fptrunc
422body:             |
423  bb.0:
424    liveins: $vgpr0_vgpr1
425    ; CHECK-LABEL: name: test_fptrunc
426    ; CHECK: liveins: $vgpr0_vgpr1
427    ; CHECK-NEXT: {{  $}}
428    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
429    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]]
430    ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FNEG]](s64)
431    ; CHECK-NEXT: $vgpr0 = COPY [[FPTRUNC]](s32)
432    %0:_(s64) = COPY $vgpr0_vgpr1
433    %1:_(s32) = G_FPTRUNC %0:_(s64)
434    %2:_(s32) = G_FNEG %1:_
435    $vgpr0 = COPY %2:_(s32)
436
437...
438---
439name:            test_amdgcn_rcp
440body:             |
441  bb.0:
442    liveins: $vgpr0
443
444    ; CHECK-LABEL: name: test_amdgcn_rcp
445    ; CHECK: liveins: $vgpr0
446    ; CHECK-NEXT: {{  $}}
447    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
448    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
449    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](s32)
450    ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
451    %0:_(s32) = COPY $vgpr0
452    %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0(s32)
453    %2:_(s32) = G_FNEG %1
454    $vgpr0 = COPY %2(s32)
455
456...
457---
458name:            test_amdgcn_rcp_legacy
459body:             |
460  bb.0:
461    liveins: $vgpr0
462
463    ; CHECK-LABEL: name: test_amdgcn_rcp_legacy
464    ; CHECK: liveins: $vgpr0
465    ; CHECK-NEXT: {{  $}}
466    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
467    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
468    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), [[FNEG]](s32)
469    ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
470    %0:_(s32) = COPY $vgpr0
471    %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0(s32)
472    %2:_(s32) = G_FNEG %1
473    $vgpr0 = COPY %2(s32)
474
475...
476---
477name:            test_amdgcn_sin
478body:             |
479  bb.0:
480    liveins: $vgpr0
481
482    ; CHECK-LABEL: name: test_amdgcn_sin
483    ; CHECK: liveins: $vgpr0
484    ; CHECK-NEXT: {{  $}}
485    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
486    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
487    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FNEG]](s32)
488    ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
489    %0:_(s32) = COPY $vgpr0
490    %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0(s32)
491    %2:_(s32) = G_FNEG %1
492    $vgpr0 = COPY %2(s32)
493
494...
495---
496name:            test_fmul_legacy
497body:             |
498  bb.0:
499    liveins: $vgpr0, $vgpr1
500
501    ; CHECK-LABEL: name: test_fmul_legacy
502    ; CHECK: liveins: $vgpr0, $vgpr1
503    ; CHECK-NEXT: {{  $}}
504    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
505    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
506    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
507    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[COPY]](s32), [[FNEG]](s32)
508    ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
509    %0:_(s32) = COPY $vgpr0
510    %1:_(s32) = COPY $vgpr1
511    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), %0(s32), %1(s32)
512    %3:_(s32) = G_FNEG %2
513    $vgpr0 = COPY %3(s32)
514
515...
516---
517name:            test_fmed3
518body:             |
519  bb.0:
520    liveins: $vgpr0, $vgpr1, $vgpr2
521
522    ; CHECK-LABEL: name: test_fmed3
523    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
524    ; CHECK-NEXT: {{  $}}
525    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
526    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
527    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
528    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
529    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
530    ; CHECK-NEXT: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]]
531    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), [[FNEG]](s32), [[FNEG1]](s32), [[FNEG2]](s32)
532    ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
533    %0:_(s32) = COPY $vgpr0
534    %1:_(s32) = COPY $vgpr1
535    %2:_(s32) = COPY $vgpr2
536    %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0(s32), %1(s32), %2(s32)
537    %4:_(s32) = G_FNEG %3
538    $vgpr0 = COPY %4(s32)
539
540...
541---
542name:            test_amdgcn_fma_legacy
543body:             |
544  bb.0:
545    liveins: $vgpr0, $vgpr1, $vgpr2
546
547    ; CHECK-LABEL: name: test_amdgcn_fma_legacy
548    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
549    ; CHECK-NEXT: {{  $}}
550    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
551    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
552    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
553    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
554    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]]
555    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), [[COPY]](s32), [[FNEG]](s32), [[FNEG1]](s32)
556    ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
557    %0:_(s32) = COPY $vgpr0
558    %1:_(s32) = COPY $vgpr1
559    %2:_(s32) = COPY $vgpr2
560    %3:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), %0(s32), %1(s32), %2(s32)
561    %4:_(s32) = G_FNEG %3
562    $vgpr0 = COPY %4(s32)
563
564...
565
566# Don't fold fneg for fadd, fsub, fma, fmad or fma_legacy without nsz
567---
568name:            test_fadd_sz
569body:             |
570  bb.0:
571    liveins: $vgpr0, $vgpr1
572
573    ; CHECK-LABEL: name: test_fadd_sz
574    ; CHECK: liveins: $vgpr0, $vgpr1
575    ; CHECK-NEXT: {{  $}}
576    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
577    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
578    ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
579    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FADD]]
580    ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
581    %0:_(s32) = COPY $vgpr0
582    %1:_(s32) = COPY $vgpr1
583    %2:_(s32) = G_FADD %0, %1
584    %3:_(s32) = G_FNEG %2
585    $vgpr0 = COPY %3(s32)
586
587...
588---
589name:            test_fsub_sz
590body:             |
591  bb.0:
592    liveins: $vgpr0, $vgpr1
593
594    ; CHECK-LABEL: name: test_fsub_sz
595    ; CHECK: liveins: $vgpr0, $vgpr1
596    ; CHECK-NEXT: {{  $}}
597    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
598    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
599    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
600    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FSUB]]
601    ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
602    %0:_(s32) = COPY $vgpr0
603    %1:_(s32) = COPY $vgpr1
604    %2:_(s32) = G_FSUB %0, %1
605    %3:_(s32) = G_FNEG %2
606    $vgpr0 = COPY %3(s32)
607
608...
609---
610name:            test_fma_sz
611body:             |
612  bb.0:
613    liveins: $vgpr0, $vgpr1, $vgpr2
614
615    ; CHECK-LABEL: name: test_fma_sz
616    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
617    ; CHECK-NEXT: {{  $}}
618    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
619    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
620    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
621    ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
622    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMA]]
623    ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
624    %0:_(s32) = COPY $vgpr0
625    %1:_(s32) = COPY $vgpr1
626    %2:_(s32) = COPY $vgpr2
627    %3:_(s32) = G_FMA %0, %1, %2
628    %4:_(s32) = G_FNEG %3
629    $vgpr0 = COPY %4(s32)
630
631...
632---
633name:            test_fmad_sz
634body:             |
635  bb.0:
636    liveins: $vgpr0, $vgpr1, $vgpr2
637
638    ; CHECK-LABEL: name: test_fmad_sz
639    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
640    ; CHECK-NEXT: {{  $}}
641    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
642    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
643    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
644    ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
645    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMAD]]
646    ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
647    %0:_(s32) = COPY $vgpr0
648    %1:_(s32) = COPY $vgpr1
649    %2:_(s32) = COPY $vgpr2
650    %3:_(s32) = G_FMAD %0, %1, %2
651    %4:_(s32) = G_FNEG %3
652    $vgpr0 = COPY %4(s32)
653
654...
655---
656name:            test_amdgcn_fma_legacy_sz
657body:             |
658  bb.0:
659    liveins: $vgpr0, $vgpr1, $vgpr2
660
661    ; CHECK-LABEL: name: test_amdgcn_fma_legacy_sz
662    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
663    ; CHECK-NEXT: {{  $}}
664    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
665    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
666    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
667    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
668    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
669    ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
670    %0:_(s32) = COPY $vgpr0
671    %1:_(s32) = COPY $vgpr1
672    %2:_(s32) = COPY $vgpr2
673    %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), %0(s32), %1(s32), %2(s32)
674    %4:_(s32) = G_FNEG %3
675    $vgpr0 = COPY %4(s32)
676
677...
678
679# Don't negate 0 for minnum, maxnum
680---
681name:            test_fminnum_zero
682body:             |
683  bb.0:
684    liveins: $vgpr0
685    ; CHECK-LABEL: name: test_fminnum_zero
686    ; CHECK: liveins: $vgpr0
687    ; CHECK-NEXT: {{  $}}
688    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
689    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
690    ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[C]]
691    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMINNUM]]
692    ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
693    %0:_(s32) = COPY $vgpr0
694    %1:_(s32) = G_FCONSTANT float 0.000000e+00
695    %2:_(s32) = G_FMINNUM %0:_, %1:_
696    %3:_(s32) = G_FNEG %2:_
697    $vgpr0 = COPY %3:_(s32)
698
699...
700
701# On VI and above don't negate 1.0 / (0.5 * pi)
702---
703name:            test_fminnum_inv2pi_half
704body:             |
705  bb.0:
706    liveins: $vgpr0
707    ; CHECK-LABEL: name: test_fminnum_inv2pi_half
708    ; CHECK: liveins: $vgpr0
709    ; CHECK-NEXT: {{  $}}
710    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
711    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
712    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
713    ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s16) = G_FMINNUM [[TRUNC]], [[C]]
714    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FMINNUM]]
715    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FNEG]](s16)
716    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
717    %0:_(s32) = COPY $vgpr0
718    %1:_(s16) = G_TRUNC %0:_(s32)
719    %2:_(s16) = G_FCONSTANT half 0xH3118
720    %3:_(s16) = G_FMINNUM %1:_, %2:_
721    %4:_(s16) = G_FNEG %3:_
722    %5:_(s32) = G_ANYEXT %4:_(s16)
723    $vgpr0 = COPY %5:_(s32)
724
725...
726---
727name:            test_fminnum_inv2pi_float
728body:             |
729  bb.0:
730    liveins: $vgpr0
731    ; CHECK-LABEL: name: test_fminnum_inv2pi_float
732    ; CHECK: liveins: $vgpr0
733    ; CHECK-NEXT: {{  $}}
734    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
735    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
736    ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[C]]
737    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMINNUM]]
738    ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
739    %0:_(s32) = COPY $vgpr0
740    %1:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
741    %2:_(s32) = G_FMINNUM %0:_, %1:_
742    %3:_(s32) = G_FNEG %2:_
743    $vgpr0 = COPY %3:_(s32)
744
745...
746---
747name:            test_fminnum_inv2pi_double
748body:             |
749  bb.0:
750    liveins: $vgpr0_vgpr1
751    ; CHECK-LABEL: name: test_fminnum_inv2pi_double
752    ; CHECK: liveins: $vgpr0_vgpr1
753    ; CHECK-NEXT: {{  $}}
754    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
755    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C882
756    ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s64) = G_FMINNUM [[COPY]], [[C]]
757    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[FMINNUM]]
758    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
759    %0:_(s64) = COPY $vgpr0_vgpr1
760    %1:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C882
761    %2:_(s64) = G_FMINNUM %0:_, %1:_
762    %3:_(s64) = G_FNEG %2:_
763    $vgpr0_vgpr1 = COPY %3:_(s64)
764
765...
766
767#Don't fold when where instruction count will not decrease.
768---
769name:            test_use_both
770body:             |
771  bb.0:
772    liveins: $vgpr0, $vgpr1, $vgpr2
773
774    ; CHECK-LABEL: name: test_use_both
775    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
776    ; CHECK-NEXT: {{  $}}
777    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
778    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
779    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
780    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
781    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
782    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FNEG]], [[COPY2]]
783    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)
784    ; CHECK-NEXT: $vgpr1 = COPY [[FNEG]](s32)
785    ; CHECK-NEXT: $vgpr2 = COPY [[FMUL1]](s32)
786    %0:_(s32) = COPY $vgpr0
787    %1:_(s32) = COPY $vgpr1
788    %2:_(s32) = COPY $vgpr2
789    %3:_(s32) = G_FMUL %0, %1
790    %4:_(s32) = G_FNEG %3
791    %5:_(s32) = G_FMUL %4, %2
792    $vgpr0 = COPY %3:_(s32)
793    $vgpr1 = COPY %4:_(s32)
794    $vgpr2 = COPY %5:_(s32)
795
796...
797
798#Don't fold when where instruction count will not decrease.
799---
800name:            test_use_both2
801body:             |
802  bb.0:
803    liveins: $vgpr0, $vgpr1
804
805    ; CHECK-LABEL: name: test_use_both2
806    ; CHECK: liveins: $vgpr0, $vgpr1
807    ; CHECK-NEXT: {{  $}}
808    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
809    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
810    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
811    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
812    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)
813    ; CHECK-NEXT: $vgpr1 = COPY [[FNEG]](s32)
814    %0:_(s32) = COPY $vgpr0
815    %1:_(s32) = COPY $vgpr1
816    %2:_(s32) = G_FMUL %0, %1
817    %3:_(s32) = G_FNEG %2
818    $vgpr0 = COPY %2:_(s32)
819    $vgpr1 = COPY %3:_(s32)
820
821...
822
823---
824name:            multiple_uses_of_fneg
825body:             |
826  bb.0:
827    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
828
829    ; CHECK-LABEL: name: multiple_uses_of_fneg
830    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
831    ; CHECK-NEXT: {{  $}}
832    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
833    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
834    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
835    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
836    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
837    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[FNEG]]
838    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FMUL]], [[COPY2]]
839    ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL]], [[COPY3]]
840    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)
841    ; CHECK-NEXT: $vgpr1 = COPY [[FMUL1]](s32)
842    ; CHECK-NEXT: $vgpr2 = COPY [[FMUL2]](s32)
843    %0:_(s32) = COPY $vgpr0
844    %1:_(s32) = COPY $vgpr1
845    %2:_(s32) = COPY $vgpr2
846    %3:_(s32) = COPY $vgpr3
847
848    %4:_(s32) = G_FMUL %0, %1
849    %5:_(s32) = G_FNEG %4
850    %6:_(s32) = G_FMUL %5, %2
851    %7:_(s32) = G_FMUL %5, %3
852
853    $vgpr0 = COPY %5:_(s32)
854    $vgpr1 = COPY %6:_(s32)
855    $vgpr2 = COPY %7:_(s32)
856
857...
858
859# Check if new fneg is inserted at the appropriate place
860---
861name:            fneg_src_has_multiple_uses
862body:             |
863  bb.0:
864    liveins: $vgpr0, $vgpr1, $vgpr2
865
866    ; CHECK-LABEL: name: fneg_src_has_multiple_uses
867    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
868    ; CHECK-NEXT: {{  $}}
869    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
870    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
871    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
872    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
873    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[FNEG]]
874    ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
875    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FNEG1]], [[COPY2]]
876    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
877    ; CHECK-NEXT: $vgpr1 = COPY [[FMUL]](s32)
878    %0:_(s32) = COPY $vgpr0
879    %1:_(s32) = COPY $vgpr1
880    %2:_(s32) = COPY $vgpr2
881    %3:_(s32) = G_FMUL %0:_, %1:_
882    %4:_(s32) = G_FMUL %3:_, %2:_
883    %5:_(s32) = G_FNEG %3:_
884    $vgpr0 = COPY %4:_(s32)
885    $vgpr1 = COPY %5:_(s32)
886
887...
888