xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll (revision 14d006c53c67ded7da00e7880c58f2c7e25ee1f1)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s
3
4define hidden <2 x i64> @icmp_v2i32_sext_to_v2i64(<2 x i32> %arg) {
5; CHECK-LABEL: icmp_v2i32_sext_to_v2i64:
6; CHECK:       ; %bb.0:
7; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
9; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
10; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
11; CHECK-NEXT:    v_bfe_i32 v0, v0, 0, 1
12; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
13; CHECK-NEXT:    v_bfe_i32 v2, v1, 0, 1
14; CHECK-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
15; CHECK-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
16; CHECK-NEXT:    s_setpc_b64 s[30:31]
17  %cmp = icmp eq <2 x i32> %arg, zeroinitializer
18  %sext = sext <2 x i1> %cmp to <2 x i64>
19  ret <2 x i64> %sext
20}
21
22define hidden <2 x i64> @icmp_v2i32_zext_to_v2i64(<2 x i32> %arg) {
23; CHECK-LABEL: icmp_v2i32_zext_to_v2i64:
24; CHECK:       ; %bb.0:
25; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
26; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
27; CHECK-NEXT:    v_mov_b32_e32 v3, 0
28; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
29; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
30; CHECK-NEXT:    v_mov_b32_e32 v1, 0
31; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
32; CHECK-NEXT:    s_setpc_b64 s[30:31]
33  %cmp = icmp eq <2 x i32> %arg, zeroinitializer
34  %sext = zext <2 x i1> %cmp to <2 x i64>
35  ret <2 x i64> %sext
36}
37