1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=WAVE64 %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=WAVE32 %s 4 5define i32 @s_andn2_i1_vcc(i32 %arg0, i32 %arg1) { 6; WAVE64-LABEL: s_andn2_i1_vcc: 7; WAVE64: ; %bb.0: 8; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 9; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 10; WAVE64-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v1 11; WAVE64-NEXT: s_and_b64 s[4:5], vcc, s[4:5] 12; WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 13; WAVE64-NEXT: s_setpc_b64 s[30:31] 14; 15; WAVE32-LABEL: s_andn2_i1_vcc: 16; WAVE32: ; %bb.0: 17; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 18; WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 19; WAVE32-NEXT: v_cmp_ne_u32_e64 s4, 0, v1 20; WAVE32-NEXT: s_and_b32 s4, vcc_lo, s4 21; WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 22; WAVE32-NEXT: s_setpc_b64 s[30:31] 23 %src0 = icmp eq i32 %arg0, 0 24 %src1 = icmp eq i32 %arg1, 0 25 %not.src1 = xor i1 %src1, true 26 %and = and i1 %src0, %not.src1 27 %select = select i1 %and, i32 1, i32 0 28 ret i32 %select 29} 30 31define i32 @s_andn2_i1_vcc_commute(i32 %arg0, i32 %arg1) { 32; WAVE64-LABEL: s_andn2_i1_vcc_commute: 33; WAVE64: ; %bb.0: 34; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 35; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 36; WAVE64-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v1 37; WAVE64-NEXT: s_and_b64 s[4:5], s[4:5], vcc 38; WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 39; WAVE64-NEXT: s_setpc_b64 s[30:31] 40; 41; WAVE32-LABEL: s_andn2_i1_vcc_commute: 42; WAVE32: ; %bb.0: 43; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 44; WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 45; WAVE32-NEXT: v_cmp_ne_u32_e64 s4, 0, v1 46; WAVE32-NEXT: s_and_b32 s4, s4, vcc_lo 47; WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 48; WAVE32-NEXT: s_setpc_b64 s[30:31] 49 %src0 = icmp eq i32 %arg0, 0 50 %src1 = icmp eq i32 %arg1, 0 51 %not.src1 = xor i1 %src1, true 52 %and = and i1 %not.src1, %src0 53 %select = select i1 %and, i32 1, i32 0 54 ret i32 %select 55} 56 57define i32 @s_andn2_i1_vcc_multi_use(i32 %arg0, i32 %arg1) { 58; WAVE64-LABEL: s_andn2_i1_vcc_multi_use: 59; WAVE64: ; %bb.0: 60; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 61; WAVE64-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v1 62; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 63; WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 64; WAVE64-NEXT: s_and_b64 s[4:5], vcc, s[4:5] 65; WAVE64-NEXT: v_cndmask_b32_e64 v0, v0, 1, s[4:5] 66; WAVE64-NEXT: s_setpc_b64 s[30:31] 67; 68; WAVE32-LABEL: s_andn2_i1_vcc_multi_use: 69; WAVE32: ; %bb.0: 70; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 71; WAVE32-NEXT: v_cmp_ne_u32_e64 s4, 0, v1 72; WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 73; WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 74; WAVE32-NEXT: s_and_b32 s4, vcc_lo, s4 75; WAVE32-NEXT: v_cndmask_b32_e64 v0, v0, 1, s4 76; WAVE32-NEXT: s_setpc_b64 s[30:31] 77 %src0 = icmp eq i32 %arg0, 0 78 %src1 = icmp eq i32 %arg1, 0 79 %not.src1 = xor i1 %src1, -1 80 %user = zext i1 %not.src1 to i32 81 %and = and i1 %src0, %not.src1 82 %select = select i1 %and, i32 1, i32 %user 83 ret i32 %select 84} 85 86define <2 x i32> @s_andn2_v2i1_vcc(<2 x i32> %arg0, <2 x i32> %arg1) { 87; WAVE64-LABEL: s_andn2_v2i1_vcc: 88; WAVE64: ; %bb.0: 89; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 90; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 91; WAVE64-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v2 92; WAVE64-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v1 93; WAVE64-NEXT: v_cmp_ne_u32_e64 s[8:9], 0, v3 94; WAVE64-NEXT: s_and_b64 s[4:5], vcc, s[4:5] 95; WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 96; WAVE64-NEXT: s_and_b64 s[4:5], s[6:7], s[8:9] 97; WAVE64-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] 98; WAVE64-NEXT: s_setpc_b64 s[30:31] 99; 100; WAVE32-LABEL: s_andn2_v2i1_vcc: 101; WAVE32: ; %bb.0: 102; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 103; WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 104; WAVE32-NEXT: v_cmp_ne_u32_e64 s4, 0, v2 105; WAVE32-NEXT: v_cmp_eq_u32_e64 s5, 0, v1 106; WAVE32-NEXT: v_cmp_ne_u32_e64 s6, 0, v3 107; WAVE32-NEXT: s_and_b32 s4, vcc_lo, s4 108; WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 109; WAVE32-NEXT: s_and_b32 s4, s5, s6 110; WAVE32-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4 111; WAVE32-NEXT: s_setpc_b64 s[30:31] 112 %src0 = icmp eq <2 x i32> %arg0, zeroinitializer 113 %src1 = icmp eq <2 x i32> %arg1, zeroinitializer 114 %not.src1 = xor <2 x i1> %src1, <i1 true, i1 true> 115 %and = and <2 x i1> %src0, %not.src1 116 %select = select <2 x i1> %and, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer 117 ret <2 x i32> %select 118} 119 120define <2 x i32> @s_andn2_v2i1_vcc_commute(<2 x i32> %arg0, <2 x i32> %arg1) { 121; WAVE64-LABEL: s_andn2_v2i1_vcc_commute: 122; WAVE64: ; %bb.0: 123; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 124; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 125; WAVE64-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v2 126; WAVE64-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v1 127; WAVE64-NEXT: v_cmp_ne_u32_e64 s[8:9], 0, v3 128; WAVE64-NEXT: s_and_b64 s[4:5], s[4:5], vcc 129; WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 130; WAVE64-NEXT: s_and_b64 s[4:5], s[8:9], s[6:7] 131; WAVE64-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] 132; WAVE64-NEXT: s_setpc_b64 s[30:31] 133; 134; WAVE32-LABEL: s_andn2_v2i1_vcc_commute: 135; WAVE32: ; %bb.0: 136; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 137; WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 138; WAVE32-NEXT: v_cmp_ne_u32_e64 s4, 0, v2 139; WAVE32-NEXT: v_cmp_eq_u32_e64 s5, 0, v1 140; WAVE32-NEXT: v_cmp_ne_u32_e64 s6, 0, v3 141; WAVE32-NEXT: s_and_b32 s4, s4, vcc_lo 142; WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 143; WAVE32-NEXT: s_and_b32 s4, s6, s5 144; WAVE32-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4 145; WAVE32-NEXT: s_setpc_b64 s[30:31] 146 %src0 = icmp eq <2 x i32> %arg0, zeroinitializer 147 %src1 = icmp eq <2 x i32> %arg1, zeroinitializer 148 %not.src1 = xor <2 x i1> %src1, <i1 true, i1 true> 149 %and = and <2 x i1> %not.src1, %src0 150 %select = select <2 x i1> %and, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer 151 ret <2 x i32> %select 152} 153 154