xref: /llvm-project/llvm/test/CodeGen/AArch64/xor.ll (revision 2e68ba99def5b07f4c6c53627baf076c5c924979) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
3
4define i32 @PR39657(ptr %p, i64 %x) {
5; CHECK-LABEL: PR39657:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    mvn x8, x1
8; CHECK-NEXT:    ldr w0, [x0, x8, lsl #2]
9; CHECK-NEXT:    ret
10  %sh = shl i64 %x, 2
11  %mul = xor i64 %sh, -4
12  %add.ptr = getelementptr inbounds i8, ptr %p, i64 %mul
13  %load = load i32, ptr %add.ptr, align 4
14  ret i32 %load
15}
16
17define i32 @add_of_not(i32 %x, i32 %y) {
18; CHECK-LABEL: add_of_not:
19; CHECK:       // %bb.0:
20; CHECK-NEXT:    mvn w8, w1
21; CHECK-NEXT:    add w0, w8, w0
22; CHECK-NEXT:    ret
23  %t0 = sub i32 %x, %y
24  %r = add i32 %t0, -1
25  ret i32 %r
26}
27
28define i32 @add_of_not_decrement(i32 %x, i32 %y) {
29; CHECK-LABEL: add_of_not_decrement:
30; CHECK:       // %bb.0:
31; CHECK-NEXT:    mvn w8, w1
32; CHECK-NEXT:    add w0, w8, w0
33; CHECK-NEXT:    ret
34  %t0 = sub i32 %x, %y
35  %r = sub i32 %t0, 1
36  ret i32 %r
37}
38
39define <4 x i32> @vec_add_of_not(<4 x i32> %x, <4 x i32> %y) {
40; CHECK-LABEL: vec_add_of_not:
41; CHECK:       // %bb.0:
42; CHECK-NEXT:    mvn v1.16b, v1.16b
43; CHECK-NEXT:    add v0.4s, v1.4s, v0.4s
44; CHECK-NEXT:    ret
45  %t0 = sub <4 x i32> %x, %y
46  %r = add <4 x i32> %t0, <i32 -1, i32 -1, i32 -1, i32 -1>
47  ret <4 x i32> %r
48}
49
50define <4 x i32> @vec_add_of_not_decrement(<4 x i32> %x, <4 x i32> %y) {
51; CHECK-LABEL: vec_add_of_not_decrement:
52; CHECK:       // %bb.0:
53; CHECK-NEXT:    mvn v1.16b, v1.16b
54; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
55; CHECK-NEXT:    ret
56  %t0 = sub <4 x i32> %x, %y
57  %r = sub <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
58  ret <4 x i32> %r
59}
60
61define <4 x i32> @vec_add_of_not_with_undef(<4 x i32> %x, <4 x i32> %y) {
62; CHECK-LABEL: vec_add_of_not_with_undef:
63; CHECK:       // %bb.0:
64; CHECK-NEXT:    mvn v1.16b, v1.16b
65; CHECK-NEXT:    add v0.4s, v1.4s, v0.4s
66; CHECK-NEXT:    ret
67  %t0 = sub <4 x i32> %x, %y
68  %r = add <4 x i32> %t0, <i32 -1, i32 undef, i32 -1, i32 -1>
69  ret <4 x i32> %r
70}
71
72define <4 x i32> @vec_add_of_not_with_undef_decrement(<4 x i32> %x, <4 x i32> %y) {
73; CHECK-LABEL: vec_add_of_not_with_undef_decrement:
74; CHECK:       // %bb.0:
75; CHECK-NEXT:    mvn v1.16b, v1.16b
76; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
77; CHECK-NEXT:    ret
78  %t0 = sub <4 x i32> %x, %y
79  %r = sub <4 x i32> %t0, <i32 1, i32 undef, i32 1, i32 1>
80  ret <4 x i32> %r
81}
82