xref: /llvm-project/llvm/test/CodeGen/AArch64/misched-bundle.mir (revision 318c69de52b61d64d5ea113dc2e9f307f7fd4d51)

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a510 -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck  %s
# REQUIRES: asserts

# CHECK:      SU(0):   renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT:   # preds left       : 0
# CHECK-NEXT:   # succs left       : 4
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 3
# CHECK-NEXT:   Depth              : 0
# CHECK-NEXT:   Height             : 7
# CHECK-NEXT:   Successors:
# CHECK-NEXT:     SU(6): Out  Latency=1
# CHECK-NEXT:     SU(6): Data Latency=3 Reg=$z0
# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
# CHECK-NEXT:   Single Issue       : false;
# CHECK-NEXT: SU(1):   renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT:   # preds left       : 0
# CHECK-NEXT:   # succs left       : 9
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 3
# CHECK-NEXT:   Depth              : 0
# CHECK-NEXT:   Height             : 7
# CHECK-NEXT:   Successors:
# CHECK-NEXT:     SU(7): Out  Latency=1
# CHECK-NEXT:     SU(7): Out  Latency=1
# CHECK-NEXT:     SU(7): Out  Latency=1
# CHECK-NEXT:     SU(7): Out  Latency=1
# CHECK-NEXT:     SU(7): Out  Latency=1
# CHECK-NEXT:     SU(7): Out  Latency=1
# CHECK-NEXT:     SU(6): Data Latency=3 Reg=$z1
# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
# CHECK-NEXT:   Single Issue       : false;
# CHECK-NEXT: SU(2):   renamable $z2 = LD1H renamable $p0, renamable $x0, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT:   # preds left       : 0
# CHECK-NEXT:   # succs left       : 3
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 3
# CHECK-NEXT:   Depth              : 0
# CHECK-NEXT:   Height             : 7
# CHECK-NEXT:   Successors:
# CHECK-NEXT:     SU(6): Data Latency=3 Reg=$z2
# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
# CHECK-NEXT:   Single Issue       : false;
# CHECK-NEXT: SU(3):   renamable $z3 = LD1H renamable $p0, renamable $x11, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT:   # preds left       : 0
# CHECK-NEXT:   # succs left       : 3
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 3
# CHECK-NEXT:   Depth              : 0
# CHECK-NEXT:   Height             : 7
# CHECK-NEXT:   Successors:
# CHECK-NEXT:     SU(7): Data Latency=3 Reg=$z3
# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
# CHECK-NEXT:   Single Issue       : false;
# CHECK-NEXT: SU(4):   renamable $z4 = LD1H renamable $p0, renamable $x12, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT:   # preds left       : 0
# CHECK-NEXT:   # succs left       : 3
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 3
# CHECK-NEXT:   Depth              : 0
# CHECK-NEXT:   Height             : 7
# CHECK-NEXT:   Successors:
# CHECK-NEXT:     SU(7): Data Latency=3 Reg=$z4
# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
# CHECK-NEXT:   Single Issue       : false;
# CHECK-NEXT: SU(5):   renamable $z5 = LD1H renamable $p0, renamable $x13, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT:   # preds left       : 0
# CHECK-NEXT:   # succs left       : 3
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 3
# CHECK-NEXT:   Depth              : 0
# CHECK-NEXT:   Height             : 7
# CHECK-NEXT:   Successors:
# CHECK-NEXT:     SU(7): Data Latency=3 Reg=$z5
# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
# CHECK-NEXT:   Single Issue       : false;
# CHECK-NEXT: SU(6):   $z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0(tied-def 0), killed renamable $z1, killed renamable $z2
# CHECK-NEXT:   # preds left       : 4
# CHECK-NEXT:   # succs left       : 7
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 4
# CHECK-NEXT:   Depth              : 3
# CHECK-NEXT:   Height             : 4
# CHECK-NEXT:   Predecessors:
# CHECK-NEXT:     SU(2): Data Latency=3 Reg=$z2
# CHECK-NEXT:     SU(1): Data Latency=3 Reg=$z1
# CHECK-NEXT:     SU(0): Out  Latency=1
# CHECK-NEXT:     SU(0): Data Latency=3 Reg=$z0
# CHECK-NEXT:   Successors:
# CHECK-NEXT:     SU(8): Data Latency=4 Reg=$z0
# CHECK-NEXT:     SU(7): Anti Latency=0
# CHECK-NEXT:     SU(7): Anti Latency=0
# CHECK-NEXT:     SU(7): Anti Latency=0
# CHECK-NEXT:     SU(7): Anti Latency=0
# CHECK-NEXT:     SU(7): Anti Latency=0
# CHECK-NEXT:     SU(7): Anti Latency=0
# CHECK-NEXT:   Single Issue       : false;
# CHECK-NEXT: SU(7):   BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit killed $z4, implicit killed $z3
# CHECK-NEXT:   # preds left       : 15
# CHECK-NEXT:   # succs left       : 1
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 1
# CHECK-NEXT:   Depth              : 3
# CHECK-NEXT:   Height             : 4
# CHECK-NEXT:   Predecessors:
# CHECK-NEXT:     SU(6): Anti Latency=0
# CHECK-NEXT:     SU(6): Anti Latency=0
# CHECK-NEXT:     SU(6): Anti Latency=0
# CHECK-NEXT:     SU(6): Anti Latency=0
# CHECK-NEXT:     SU(6): Anti Latency=0
# CHECK-NEXT:     SU(6): Anti Latency=0
# CHECK-NEXT:     SU(5): Data Latency=3 Reg=$z5
# CHECK-NEXT:     SU(4): Data Latency=3 Reg=$z4
# CHECK-NEXT:     SU(3): Data Latency=3 Reg=$z3
# CHECK-NEXT:     SU(1): Out  Latency=1
# CHECK-NEXT:     SU(1): Out  Latency=1
# CHECK-NEXT:     SU(1): Out  Latency=1
# CHECK-NEXT:     SU(1): Out  Latency=1
# CHECK-NEXT:     SU(1): Out  Latency=1
# CHECK-NEXT:     SU(1): Out  Latency=1
# CHECK-NEXT:   Successors:
# CHECK-NEXT:     SU(9): Data Latency=4 Reg=$z1
# CHECK-NEXT:   Single Issue       : false;
# CHECK-NEXT: SU(8):   ST1H killed renamable $z0, renamable $p0, renamable $x0, renamable $x10 :: (store unknown-size, align 1)
# CHECK-NEXT:   # preds left       : 7
# CHECK-NEXT:   # succs left       : 1
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 1
# CHECK-NEXT:   Depth              : 7
# CHECK-NEXT:   Height             : 0
# CHECK-NEXT:   Predecessors:
# CHECK-NEXT:     SU(6): Data Latency=4 Reg=$z0
# CHECK-NEXT:     SU(5): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(4): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(3): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(2): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(1): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(0): Ord  Latency=0 Memory
# CHECK-NEXT:   Successors:
# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
# CHECK-NEXT:   Single Issue       : false;
# CHECK-NEXT: SU(9):   ST1H killed renamable $z1, renamable $p0, renamable $x13, renamable $x10 :: (store unknown-size, align 1)
# CHECK-NEXT:   # preds left       : 8
# CHECK-NEXT:   # succs left       : 0
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 1
# CHECK-NEXT:   Depth              : 7
# CHECK-NEXT:   Height             : 0
# CHECK-NEXT:   Predecessors:
# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(7): Data Latency=4 Reg=$z1
# CHECK-NEXT:     SU(5): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(4): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(3): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(2): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(1): Ord  Latency=0 Memory
# CHECK-NEXT:     SU(0): Ord  Latency=0 Memory
# CHECK-NEXT:   Single Issue       : false;
# CHECK-NEXT: ExitSU:   RET_ReallyLR
# CHECK-NEXT:   # preds left       : 0
# CHECK-NEXT:   # succs left       : 0
# CHECK-NEXT:   # rdefs left       : 0
# CHECK-NEXT:   Latency            : 0
# CHECK-NEXT:   Depth              : 0
# CHECK-NEXT:   Height             : 0

---
name:            test
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $p0, $x0, $x1, $x2, $x10, $x11, $x12, $x13


    ; CHECK-LABEL: name: test
    ; CHECK: liveins: $p0, $x0, $x1, $x2, $x10, $x11, $x12, $x13
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size, align 1)
    ; CHECK-NEXT: renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size, align 1)
    ; CHECK-NEXT: renamable $z2 = LD1H renamable $p0, renamable $x0, renamable $x10 :: (load unknown-size, align 1)
    ; CHECK-NEXT: renamable $z3 = LD1H renamable $p0, renamable $x11, renamable $x10 :: (load unknown-size, align 1)
    ; CHECK-NEXT: renamable $z4 = LD1H renamable $p0, renamable $x12, renamable $x10 :: (load unknown-size, align 1)
    ; CHECK-NEXT: renamable $z5 = LD1H renamable $p0, renamable $x13, renamable $x10 :: (load unknown-size, align 1)
    ; CHECK-NEXT: $z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0, killed renamable $z1, killed renamable $z2
    ; CHECK-NEXT: BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit killed $z4, implicit killed $z3 {
    ; CHECK-NEXT:   $z1 = MOVPRFX_ZZ $z5
    ; CHECK-NEXT:   $z1 = FMLA_ZPmZZ_H renamable $p0, internal killed $z1, killed renamable $z4, killed renamable $z3
    ; CHECK-NEXT: }
    ; CHECK-NEXT: ST1H killed renamable $z0, renamable $p0, renamable $x0, renamable $x10 :: (store unknown-size, align 1)
    ; CHECK-NEXT: ST1H killed renamable $z1, renamable $p0, renamable $x13, renamable $x10 :: (store unknown-size, align 1)
    ; CHECK-NEXT: RET_ReallyLR
    renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size)
    renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size)
    renamable $z2 = LD1H renamable $p0, renamable $x0, renamable $x10 :: (load unknown-size)
    renamable $z3 = LD1H renamable $p0, renamable $x11, renamable $x10 :: (load unknown-size)
    renamable $z4 = LD1H renamable $p0, renamable $x12, renamable $x10 :: (load unknown-size)
    renamable $z5 = LD1H renamable $p0, renamable $x13, renamable $x10 :: (load unknown-size)
    $z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0, killed renamable $z1, killed renamable $z2
    BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit killed $z4, implicit killed $z3 {
        $z1 = MOVPRFX_ZZ $z5
        $z1 = FMLA_ZPmZZ_H renamable $p0, internal killed $z1, killed renamable $z4, killed renamable $z3
    }
    ST1H killed renamable $z0, renamable $p0, renamable $x0, renamable $x10 :: (store unknown-size)
    ST1H killed renamable $z1, renamable $p0, renamable $x13, renamable $x10 :: (store unknown-size)
    RET_ReallyLR

...