xref: /llvm-project/llvm/test/CodeGen/AArch64/misched-bundle.mir (revision 318c69de52b61d64d5ea113dc2e9f307f7fd4d51) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a510 -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck  %s
3# REQUIRES: asserts
4
5# CHECK:      SU(0):   renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size, align 1)
6# CHECK-NEXT:   # preds left       : 0
7# CHECK-NEXT:   # succs left       : 4
8# CHECK-NEXT:   # rdefs left       : 0
9# CHECK-NEXT:   Latency            : 3
10# CHECK-NEXT:   Depth              : 0
11# CHECK-NEXT:   Height             : 7
12# CHECK-NEXT:   Successors:
13# CHECK-NEXT:     SU(6): Out  Latency=1
14# CHECK-NEXT:     SU(6): Data Latency=3 Reg=$z0
15# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
16# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
17# CHECK-NEXT:   Single Issue       : false;
18# CHECK-NEXT: SU(1):   renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size, align 1)
19# CHECK-NEXT:   # preds left       : 0
20# CHECK-NEXT:   # succs left       : 9
21# CHECK-NEXT:   # rdefs left       : 0
22# CHECK-NEXT:   Latency            : 3
23# CHECK-NEXT:   Depth              : 0
24# CHECK-NEXT:   Height             : 7
25# CHECK-NEXT:   Successors:
26# CHECK-NEXT:     SU(7): Out  Latency=1
27# CHECK-NEXT:     SU(7): Out  Latency=1
28# CHECK-NEXT:     SU(7): Out  Latency=1
29# CHECK-NEXT:     SU(7): Out  Latency=1
30# CHECK-NEXT:     SU(7): Out  Latency=1
31# CHECK-NEXT:     SU(7): Out  Latency=1
32# CHECK-NEXT:     SU(6): Data Latency=3 Reg=$z1
33# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
34# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
35# CHECK-NEXT:   Single Issue       : false;
36# CHECK-NEXT: SU(2):   renamable $z2 = LD1H renamable $p0, renamable $x0, renamable $x10 :: (load unknown-size, align 1)
37# CHECK-NEXT:   # preds left       : 0
38# CHECK-NEXT:   # succs left       : 3
39# CHECK-NEXT:   # rdefs left       : 0
40# CHECK-NEXT:   Latency            : 3
41# CHECK-NEXT:   Depth              : 0
42# CHECK-NEXT:   Height             : 7
43# CHECK-NEXT:   Successors:
44# CHECK-NEXT:     SU(6): Data Latency=3 Reg=$z2
45# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
46# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
47# CHECK-NEXT:   Single Issue       : false;
48# CHECK-NEXT: SU(3):   renamable $z3 = LD1H renamable $p0, renamable $x11, renamable $x10 :: (load unknown-size, align 1)
49# CHECK-NEXT:   # preds left       : 0
50# CHECK-NEXT:   # succs left       : 3
51# CHECK-NEXT:   # rdefs left       : 0
52# CHECK-NEXT:   Latency            : 3
53# CHECK-NEXT:   Depth              : 0
54# CHECK-NEXT:   Height             : 7
55# CHECK-NEXT:   Successors:
56# CHECK-NEXT:     SU(7): Data Latency=3 Reg=$z3
57# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
58# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
59# CHECK-NEXT:   Single Issue       : false;
60# CHECK-NEXT: SU(4):   renamable $z4 = LD1H renamable $p0, renamable $x12, renamable $x10 :: (load unknown-size, align 1)
61# CHECK-NEXT:   # preds left       : 0
62# CHECK-NEXT:   # succs left       : 3
63# CHECK-NEXT:   # rdefs left       : 0
64# CHECK-NEXT:   Latency            : 3
65# CHECK-NEXT:   Depth              : 0
66# CHECK-NEXT:   Height             : 7
67# CHECK-NEXT:   Successors:
68# CHECK-NEXT:     SU(7): Data Latency=3 Reg=$z4
69# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
70# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
71# CHECK-NEXT:   Single Issue       : false;
72# CHECK-NEXT: SU(5):   renamable $z5 = LD1H renamable $p0, renamable $x13, renamable $x10 :: (load unknown-size, align 1)
73# CHECK-NEXT:   # preds left       : 0
74# CHECK-NEXT:   # succs left       : 3
75# CHECK-NEXT:   # rdefs left       : 0
76# CHECK-NEXT:   Latency            : 3
77# CHECK-NEXT:   Depth              : 0
78# CHECK-NEXT:   Height             : 7
79# CHECK-NEXT:   Successors:
80# CHECK-NEXT:     SU(7): Data Latency=3 Reg=$z5
81# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
82# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
83# CHECK-NEXT:   Single Issue       : false;
84# CHECK-NEXT: SU(6):   $z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0(tied-def 0), killed renamable $z1, killed renamable $z2
85# CHECK-NEXT:   # preds left       : 4
86# CHECK-NEXT:   # succs left       : 7
87# CHECK-NEXT:   # rdefs left       : 0
88# CHECK-NEXT:   Latency            : 4
89# CHECK-NEXT:   Depth              : 3
90# CHECK-NEXT:   Height             : 4
91# CHECK-NEXT:   Predecessors:
92# CHECK-NEXT:     SU(2): Data Latency=3 Reg=$z2
93# CHECK-NEXT:     SU(1): Data Latency=3 Reg=$z1
94# CHECK-NEXT:     SU(0): Out  Latency=1
95# CHECK-NEXT:     SU(0): Data Latency=3 Reg=$z0
96# CHECK-NEXT:   Successors:
97# CHECK-NEXT:     SU(8): Data Latency=4 Reg=$z0
98# CHECK-NEXT:     SU(7): Anti Latency=0
99# CHECK-NEXT:     SU(7): Anti Latency=0
100# CHECK-NEXT:     SU(7): Anti Latency=0
101# CHECK-NEXT:     SU(7): Anti Latency=0
102# CHECK-NEXT:     SU(7): Anti Latency=0
103# CHECK-NEXT:     SU(7): Anti Latency=0
104# CHECK-NEXT:   Single Issue       : false;
105# CHECK-NEXT: SU(7):   BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit killed $z4, implicit killed $z3
106# CHECK-NEXT:   # preds left       : 15
107# CHECK-NEXT:   # succs left       : 1
108# CHECK-NEXT:   # rdefs left       : 0
109# CHECK-NEXT:   Latency            : 1
110# CHECK-NEXT:   Depth              : 3
111# CHECK-NEXT:   Height             : 4
112# CHECK-NEXT:   Predecessors:
113# CHECK-NEXT:     SU(6): Anti Latency=0
114# CHECK-NEXT:     SU(6): Anti Latency=0
115# CHECK-NEXT:     SU(6): Anti Latency=0
116# CHECK-NEXT:     SU(6): Anti Latency=0
117# CHECK-NEXT:     SU(6): Anti Latency=0
118# CHECK-NEXT:     SU(6): Anti Latency=0
119# CHECK-NEXT:     SU(5): Data Latency=3 Reg=$z5
120# CHECK-NEXT:     SU(4): Data Latency=3 Reg=$z4
121# CHECK-NEXT:     SU(3): Data Latency=3 Reg=$z3
122# CHECK-NEXT:     SU(1): Out  Latency=1
123# CHECK-NEXT:     SU(1): Out  Latency=1
124# CHECK-NEXT:     SU(1): Out  Latency=1
125# CHECK-NEXT:     SU(1): Out  Latency=1
126# CHECK-NEXT:     SU(1): Out  Latency=1
127# CHECK-NEXT:     SU(1): Out  Latency=1
128# CHECK-NEXT:   Successors:
129# CHECK-NEXT:     SU(9): Data Latency=4 Reg=$z1
130# CHECK-NEXT:   Single Issue       : false;
131# CHECK-NEXT: SU(8):   ST1H killed renamable $z0, renamable $p0, renamable $x0, renamable $x10 :: (store unknown-size, align 1)
132# CHECK-NEXT:   # preds left       : 7
133# CHECK-NEXT:   # succs left       : 1
134# CHECK-NEXT:   # rdefs left       : 0
135# CHECK-NEXT:   Latency            : 1
136# CHECK-NEXT:   Depth              : 7
137# CHECK-NEXT:   Height             : 0
138# CHECK-NEXT:   Predecessors:
139# CHECK-NEXT:     SU(6): Data Latency=4 Reg=$z0
140# CHECK-NEXT:     SU(5): Ord  Latency=0 Memory
141# CHECK-NEXT:     SU(4): Ord  Latency=0 Memory
142# CHECK-NEXT:     SU(3): Ord  Latency=0 Memory
143# CHECK-NEXT:     SU(2): Ord  Latency=0 Memory
144# CHECK-NEXT:     SU(1): Ord  Latency=0 Memory
145# CHECK-NEXT:     SU(0): Ord  Latency=0 Memory
146# CHECK-NEXT:   Successors:
147# CHECK-NEXT:     SU(9): Ord  Latency=0 Memory
148# CHECK-NEXT:   Single Issue       : false;
149# CHECK-NEXT: SU(9):   ST1H killed renamable $z1, renamable $p0, renamable $x13, renamable $x10 :: (store unknown-size, align 1)
150# CHECK-NEXT:   # preds left       : 8
151# CHECK-NEXT:   # succs left       : 0
152# CHECK-NEXT:   # rdefs left       : 0
153# CHECK-NEXT:   Latency            : 1
154# CHECK-NEXT:   Depth              : 7
155# CHECK-NEXT:   Height             : 0
156# CHECK-NEXT:   Predecessors:
157# CHECK-NEXT:     SU(8): Ord  Latency=0 Memory
158# CHECK-NEXT:     SU(7): Data Latency=4 Reg=$z1
159# CHECK-NEXT:     SU(5): Ord  Latency=0 Memory
160# CHECK-NEXT:     SU(4): Ord  Latency=0 Memory
161# CHECK-NEXT:     SU(3): Ord  Latency=0 Memory
162# CHECK-NEXT:     SU(2): Ord  Latency=0 Memory
163# CHECK-NEXT:     SU(1): Ord  Latency=0 Memory
164# CHECK-NEXT:     SU(0): Ord  Latency=0 Memory
165# CHECK-NEXT:   Single Issue       : false;
166# CHECK-NEXT: ExitSU:   RET_ReallyLR
167# CHECK-NEXT:   # preds left       : 0
168# CHECK-NEXT:   # succs left       : 0
169# CHECK-NEXT:   # rdefs left       : 0
170# CHECK-NEXT:   Latency            : 0
171# CHECK-NEXT:   Depth              : 0
172# CHECK-NEXT:   Height             : 0
173
174---
175name:            test
176alignment:       4
177tracksRegLiveness: true
178body:             |
179  bb.0.entry:
180    liveins: $p0, $x0, $x1, $x2, $x10, $x11, $x12, $x13
181
182
183    ; CHECK-LABEL: name: test
184    ; CHECK: liveins: $p0, $x0, $x1, $x2, $x10, $x11, $x12, $x13
185    ; CHECK-NEXT: {{  $}}
186    ; CHECK-NEXT: renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size, align 1)
187    ; CHECK-NEXT: renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size, align 1)
188    ; CHECK-NEXT: renamable $z2 = LD1H renamable $p0, renamable $x0, renamable $x10 :: (load unknown-size, align 1)
189    ; CHECK-NEXT: renamable $z3 = LD1H renamable $p0, renamable $x11, renamable $x10 :: (load unknown-size, align 1)
190    ; CHECK-NEXT: renamable $z4 = LD1H renamable $p0, renamable $x12, renamable $x10 :: (load unknown-size, align 1)
191    ; CHECK-NEXT: renamable $z5 = LD1H renamable $p0, renamable $x13, renamable $x10 :: (load unknown-size, align 1)
192    ; CHECK-NEXT: $z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0, killed renamable $z1, killed renamable $z2
193    ; CHECK-NEXT: BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit killed $z4, implicit killed $z3 {
194    ; CHECK-NEXT:   $z1 = MOVPRFX_ZZ $z5
195    ; CHECK-NEXT:   $z1 = FMLA_ZPmZZ_H renamable $p0, internal killed $z1, killed renamable $z4, killed renamable $z3
196    ; CHECK-NEXT: }
197    ; CHECK-NEXT: ST1H killed renamable $z0, renamable $p0, renamable $x0, renamable $x10 :: (store unknown-size, align 1)
198    ; CHECK-NEXT: ST1H killed renamable $z1, renamable $p0, renamable $x13, renamable $x10 :: (store unknown-size, align 1)
199    ; CHECK-NEXT: RET_ReallyLR
200    renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size)
201    renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size)
202    renamable $z2 = LD1H renamable $p0, renamable $x0, renamable $x10 :: (load unknown-size)
203    renamable $z3 = LD1H renamable $p0, renamable $x11, renamable $x10 :: (load unknown-size)
204    renamable $z4 = LD1H renamable $p0, renamable $x12, renamable $x10 :: (load unknown-size)
205    renamable $z5 = LD1H renamable $p0, renamable $x13, renamable $x10 :: (load unknown-size)
206    $z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0, killed renamable $z1, killed renamable $z2
207    BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit killed $z4, implicit killed $z3 {
208        $z1 = MOVPRFX_ZZ $z5
209        $z1 = FMLA_ZPmZZ_H renamable $p0, internal killed $z1, killed renamable $z4, killed renamable $z3
210    }
211    ST1H killed renamable $z0, renamable $p0, renamable $x0, renamable $x10 :: (store unknown-size)
212    ST1H killed renamable $z1, renamable $p0, renamable $x13, renamable $x10 :: (store unknown-size)
213    RET_ReallyLR
214
215...
216